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參數(shù)資料
| 型號： | KSZ8995XA |
| 廠商： | MICREL INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | Integrated 5-Port 10/100 QoS Switch |
| 中文描述： | DATACOM, LAN SWITCHING CIRCUIT, PQFP128 |
| 封裝： | LEAD FREE, PLASTIC, QFP-128 |
| 文件頁數(shù)： | 36/51頁 |
| 文件大?。?/td> | 305K |
| 代理商： | KSZ8995XA |
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KS8995XA
Register 23 (0x17): Port 1 Control 7
Register 39 (0x27): Port 2 Control 7
Register 55 (0x37): Port 3 Control 7
Register 71 (0x47): Port 4 Control 7
Register 87 (0x57): Port 5 Control 7
Address
7-4
rate control [11:8]
Micrel, Inc.
M9999-051305
36
May 2005
Name
Transmit low priority
Description
This along with port control 6, bits [7:0] form a 12-bit
field to determine how many “32Kbps” low priority
blocks can be transmitted (in a unit of 4K bytes in a
one second period).
This along with port control 5, bits [7:0] form a 12-bit
field to determine how many “32Kbps” high priority
blocks can be transmitted (in unit of 4K bytes in a
one second period).
Mode
R/W
Default
0
3-0
Transmit high priority
rate control [11:8]
R/W
0
Register 24 (0x18): Port 1 Control 8
Register 40 (0x28): Port 2 Control 8
Register 56 (0x38): Port 3 Control 8
Register 72 (0x48): Port 4 Control 8
Register 88 (0x58): Port 5 Control 8
Address
7-0
rate control [7:0]
Name
Receive high priority
Description
This along with port control 10, bits [3:0] form a 12-bit
field to determine how many “32Kbps” high priority
blocks can be received (in a unit of 4K bytes in a one
second period).
Mode
R/W
Default
0
Register 25 (0x19): Port 1 Control 9
Register 41 (0x29): Port 2 Control 9
Register 57 (0x39): Port 3 Control 9
Register 73 (0x49): Port 4 Control 9
Register 89 (0x59): Port 5 Control 9
Address
7-0
rate control [7:0]
Name
Receive low priority
Description
This along with port control 10, bits [7:4] form a 12-bit
field to determine how many “32Kbps” low priority
blocks can be received (in a unit of 4K bytes in a one
second period).
Mode
R/W
Default
0
Register 26 (0x1A): Port 1 Control 10
Register 42 (0x2A): Port 2 Control 10
Register 58 (0x3A): Port 3 Control 10
Register 74 (0x4A): Port 4 Control 10
Register 90 (0x5A): Port 5 Control 10
Address
7-4
rate control [11:8]
Name
Receive low priority
Description
This along with port control 9, bits [7:0] form a 12-bit
field to determine how many “32Kbps” low priority
blocks can be received (in a unit of 4K bytes in a one
second period).
This along with port control 8, bits [7:0] form a 12-bit
field to determine how many “32Kbps” high priority
blocks can be received (in a unit of 4K bytes in a one
second period).
Mode
R/W
Default
0
3-0
Receive high priority
rate control [11:8]
R/W
0
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