參數(shù)資料
型號: KSZ8995XA
廠商: MICREL INC
元件分類: 網(wǎng)絡(luò)接口
英文描述: Integrated 5-Port 10/100 QoS Switch
中文描述: DATACOM, LAN SWITCHING CIRCUIT, PQFP128
封裝: LEAD FREE, PLASTIC, QFP-128
文件頁數(shù): 32/51頁
文件大?。?/td> 305K
代理商: KSZ8995XA
KS8995XA
Micrel, Inc.
M9999-051305
32
May 2005
Address
Register 5 (0x05): Global Control 3
(continued)
1
0
Name
Description
Mode
Default
Reserved
Sniff mode select
Reserved
1 = will do Rx AND Tx sniff (both source port and
destination port need to match).
0 = will do Rx OR Tx sniff (either source port or
destination port needs to match). This is the mode
used to implement Rx only sniff.
R/W
R/W
0
0
Register 6 (0x06): Global Control 4
7
pressure enable
Switch MII back
1 = enable half-duplex back pressure on switch MII
interface.
0 = disable back pressure on switch MII interface.
1 = enable MII interface half-duplex mode.
0 = enable MII interface full-duplex mode.
R/W
0
6
Switch MII half
duplex mode
R/W
Pin SMRXD2 strap
option. Pull-down (0):
Full-duplex mode.
Pull-up (1): Half-
duplex mode.
Note: SMRXD2
has internal pull-
down.
Pin SMRXD3 strap
option. Pull-down
(0): disable flow
control. Pull-up (1):
enable flow control
Note: SMRXD3
has internal pull-
down.
Pin SMRXD1 strap
option. Pull-down (0):
Enable 100Mbps
Pull-up (1): Enable
10Mpbs.
Note: SMRXD1 has
internal pull-down.
0
5
Switch MII flow
control enable
1 = enable full-duplex flow control on switch MII interface.
0 = disable full-duplex flow control on switch MII interface.
R/W
4
Switch MII 10BT
1 = the switch interface is in 10Mbps mode.
0 = the switch interface is in 100Mbps mode.
R/W
3
Null VID replacement
1 = will replace null VID with port VID (12 bits).
0 = no replacement for null VID.
This along with the next register determines how many
“64 byte blocks” of packet data allowed on an input
port in a preset period. The period is 50ms for 100BT
or 500ms for 10BT. The default is 1%.
R/W
2-0
Broadcast storm
protection rate bit [10:8]
R/W
000
Register 7 (0x07): Global Control 5
7-0
protection rate bit [7:0]
Broadcast storm
This along with the previous register determines how
many “64 byte blocks” of packet data are allowed on
an input port in a preset period. The period is 50ms
for 100BT or 500ms for 10BT. The default is 1%.
R/W
0x4A
(1)
Note:
1. 148,800 frames/sec
×
50ms/interval
×
1% = 74 frames/interval (approx.) = 0x4A.
Register 8 (0x08): Global Control 6
7-0
Register 9 (0x09): Global Control 7
7-0
Register 10 (0x0A): Global Control 8
7-0
Factory testing
Reserved
R/W
0x24
Factory testing
Reserved
R/W
0x24
Factory testing
Reserved
R/W
0x24
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