參數(shù)資料
型號: KSZ8995FQ
廠商: Micrel Inc
文件頁數(shù): 40/89頁
文件大?。?/td> 0K
描述: IC SWITCH 10/100 5PORT 128-PQFP
標(biāo)準(zhǔn)包裝: 66
系列: *
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
配用: 576-3872-ND - BOARD EVALUATION FOR KSZ8995FQ
其它名稱: 576-3077
Micrel, Inc.
KS8995MA/FQ
October 2011
45
M9999-102611-3.0
SPIQ
SPIC
SPID
SPIS_N
0000
001
0
X
A7 A6 A5 A4 A3 A2 A1 A0
WRITE COMMAND
WRITE ADDRESS
Byte 1
D2
D0
D1
D3
D4
D5
D6
D7
SPIQ
SPIC
SPID
SPIS_N
D7
D6
D5
D4
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Byte 2
Byte 3 ...
Byte N
D2
D0
D1
D3
D4
D5
D6
D7
Figure 11. SPI Multiple Write
SPIQ
SPIC
SPID
SPIS_N
000
0
001
1
X
A7 A6 A5 A4 A3 A2 A1 A0
D7
D6
D5
D4
D3
D2
D1
D0
READ COMMAND
READ ADDRESS
Byte 1
XXX
XXXXX
XX
X
Byte 2
Byte 3 ...
Byte N
X
XX
XXXXX
X
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
SPIQ
SPIC
SPID
SPIS_N
Figure 12. SPI Multiple Read
MII Management Interface (MIIM)
A standard MIIM interface is provided for all five PHY devices in the KS8995MA/FQ. An external device with
MDC/MDIO capability is able to read PHY status or to configure PHY settings. The device is able to meet IEEE
specification of 2.5MHz MDC clock. For details on the MIIM interface standard please reference the IEEE 802.3
specification (section 22.2.4.5). The MIIM interface does not have access to all the configuration registers in the
KS8995MA/FQ. It can only access the standard MII registers. See “MIIM Registers.” The SPI interface, on the other
hand, can be used to access the entire KS8995MA/FQ feature set.
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