參數(shù)資料
型號(hào): KSZ9021GQI
廠商: Micrel Inc
文件頁(yè)數(shù): 1/59頁(yè)
文件大小: 0K
描述: TXRX GIG ETH GMII/MII 128-PQFP
標(biāo)準(zhǔn)包裝: 66
類型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 8/8
規(guī)程: 千兆位以太網(wǎng)
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤
其它名稱: 576-3790
KSZ9021GQ
Gigabit Ethernet Transceiver
with GMII / MII Support
LinkMD is a registered trademark of Micrel, Inc.
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (
408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com
September 2010
M9999-091010-1.2
General Description
The KSZ9021GQ is a completely integrated triple speed
(10Base-T/100Base-TX/1000Base-T) Ethernet Physical
Layer Transceiver for transmission and reception of data
on standard CAT-5 unshielded twisted pair (UTP) cable.
The KSZ9021GQ provides the industry standard GMII/MII
(Gigabit Media Independent Interface / Media Independent
Interface) for direct connection to GMII/MII MACs in
Gigabit Ethernet Processors and Switches for data transfer
at 1000 Mbps or 10/100 Mbps speed.
The KSZ9021GQ reduces board cost and simplifies board
layout by using on-chip termination resistors for the four
differential pairs and by integrating a LDO controller to
drive a low cost MOSFET to supply the 1.2V core.
The KSZ9021GQ provides diagnostic features to facilitate
system bring-up and debugging in production testing and
in product deployment. Parametric NAND tree support
enables fault detection between KSZ9021 I/Os and board.
Micrel LinkMD
TDR-based cable diagnostics permit
identification of faulty copper cabling. Remote and local
loopback functions provide verification of analog and
digital data paths.
The KSZ9021GQ is available in a 128-pin, lead-free PQFP
package (See Ordering Information).
Features
Single-chip 10/100/1000 Mbps IEEE 802.3 compliant
Ethernet Transceiver
GMII/MII standard compliant interface
Auto-negotiation to automatically select the highest link
up speed (10/100/100 Mbps) and duplex (half/full)
On-chip termination resistors for the differential pairs
On-chip LDO controller to support single 3.3V supply
operation – requires only external FET to generate 1.2V
for the core
Jumbo frame support up to 16KB
125MHz Reference Clock Output
Programmable LED outputs for link, activity and speed
Baseline Wander Correction
LinkMD TDR-based cable diagnostics for identification
of faulty copper cabling
Parametric NAND Tree support for fault detection
between chip I/Os and board.
Loopback modes for diagnostics
Automatic MDI/MDI-X crossover for detection and
correction of pair swap at all speeds of operation
____________________________________________________________________________________________________________
Functional Diagram
MA
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IC
S
RJ
-4
5
CONNECT
OR
ON-CHI
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T
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RM
IN
AT
IO
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RESISTO
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