參數(shù)資料
型號: KSZ8993MLI
廠商: Micrel Inc
文件頁數(shù): 44/86頁
文件大小: 0K
描述: IC SWITCH 10/100 3PORT 128-PQFP
標(biāo)準(zhǔn)包裝: 66
系列: *
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
其它名稱: 576-3350
Micrel, Inc.
KSZ8993M/ML
October 2008
49
M9999-020606
Register 1 (0x01): Chip ID1 / Start Switch
Bit
Name
R/W
Description
Default
7-4
Chip ID
RO
0x0 is assigned to M series. (93M)
0x0
3-1
Revision ID
RO
Revision ID
-
0
Start switch
RW
= 1, start the chip when external pins
(PS1, PS0) = (0,1) or (1,0) or (1,1).
Note: In (PS1, PS0) = (0, 0) mode, the chip will start
automatically after trying to read the external
EEPROM. If EEPROM does not exist, the chip will
use pin strapping and default values for all internal
registers. If EEPROM is present, the contents in the
EEPROM will be checked. The switch will check: (1)
Register 0 = 0x93, (2) Register 1 bits [7:4] = 0x0. If
this check is OK, the contents in the EEPROM will
override chip registers’ default values.
= 0, chip will not start when external pins
(PS1, PS0) = (0,1) or (1,0) or (1,1).
-
Register 2 (0x02): Global Control 0
Bit
Name
R/W
Description
Default
7
New back-off
Enable
R/W
New back-off algorithm designed for UNH
1 = Enable
0 = Disable
0x0
6-4
802.1p base
priority
R/W
Used to classify priority for incoming 802.1Q packets.
“user priority” is compared against this value.
>= : classified as high priority
<
: classified as low priority
0x4
3
Pass flow
control packet
R/W
= 1, switch will not filter 802.1x “flow control” packets
0x0
2
Buffer share
mode
R/W
= 1, buffer pool is shared by all ports. A port can use
more buffers when other ports are not busy.
= 0, a port is only allowed to use 1/3 of the buffer
pool.
0x1
1
Reserved
R/W
Reserved
0
Link change
age
R/W
= 1, link change from “l(fā)ink” to “no link” will cause fast
aging (<800us) to age
address table faster. After
an age cycle is complete, the age logic will return to
normal aging (about 200 sec).
Note: If any port is unplugged, all addresses will be
automatically aged out.
0
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