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參數(shù)資料
| 型號(hào)： | KSZ8993MLI |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 36/86頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC SWITCH 10/100 3PORT 128-PQFP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 系列： | * |
| 產(chǎn)品目錄頁(yè)面： | 1081 (CN2011-ZH PDF) |
| 其它名稱： | 576-3350 |
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Micrel, Inc.
KSZ8993M/ML
October 2008
41
M9999-020606
SPI multiple read is initiated when the master device continues to drive the KSZ8993M SPIS_N input pin (SPI
Slave Select signal) low after a byte (a register) is read. The KSZ8993M internal address counter will increment
automatically to the next byte (next register) after the read. The next byte at the next register address will be
shifted out onto the KSZ8993M SPIQ output pin. SPI multiple read will continue until the SPI master device
terminates it by de-asserting the SPIS_N signal to the KSZ8993M.
Similarly, SPI multiple write is initiated when the master device continues to drive the KSZ8993M SPIS_N input
pin low after a byte (a register) is written. The KSZ8993M internal address counter will increment automatically to
the next byte (next register) after the write. The next byte that is sent from the master device to the KSZ8993M
SDA input pin will be written to the next register address. SPI multiple write will continue until the SPI master
device terminates it by de-asserting the SPIS_N signal to the KSZ8993M.
For both SPI multiple read and multiple write, the KSZ8993M internal address counter will wrap back to register
address zero once the highest register address is reached. This feature allows all 128 KSZ8993M registers to be
read, or written with a single SPI command and any initial register address.
The KSZ8993M is capable of supporting a 5MHz SPI bus.
The following is a sample procedure for programming the KSZ8993M using the SPI bus:
1.
At the board level, connect the KSZ8993M pins as follows:
KSZ8993M Pin #
KSZ8993M Signal Name
External Processor Signal Description
99
SPIS_N
SPI Slave Select
97
SCL
(SPIC)
SPI Clock
98
SDA
(SPID)
SPI Data
(Master output; Slave input)
96
SPIQ
SPI Data
(Master input; Slave output)
Table 11. KSZ8993M SPI Connections
2.
Enable SPI slave mode by setting the KSZ8993M strap-in pins PS[1:0] (pins 100 and 101, respectively) to
“10”.
3.
Power up the board and assert reset to the KSZ8993M.
After reset, the “Start Switch” bit (register 1 bit 0) will be set to ‘0’.
4.
Configure the desired register settings in the KSZ8993M, using the SPI write or multiple write command.
5.
Read back and verify the register settings in the KSZ8993M, using the SPI read or multiple read command.
6.
Write a ‘1’ to the “Start Switch” bit to start the KSZ8993M with the programmed settings.
Note: The “Start Switch” bit cannot be set to ‘0’ to stop the switch after an ‘1’ is written to this bit. Thus, it is
recommended that all switch configuration settings are programmed before the “Start Switch” bit is set to ‘1’.
Some of the configuration settings, such as “Aging enable”, “Auto Negotiation Enable”, “Force Speed” and “Power
down” can be programmed after the switch has been started.
The following four figures illustrate the SPI data cycles for “Write”, “Read”, “Multiple Write” and “Multiple Read”.
The read data is registered out of SPIQ on the falling edge of SPIC, and the data input on SPID is registered on
the rising edge of SPIC.
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