參數(shù)資料
型號(hào): KSZ8873MLLI
廠商: Micrel Inc
文件頁數(shù): 77/115頁
文件大?。?/td> 0K
描述: IC ETHERNET SWITCH 3PORT 64LQFP
產(chǎn)品培訓(xùn)模塊: KSZ8873 Ethernet Switches
標(biāo)準(zhǔn)包裝: 160
控制器類型: 以太網(wǎng)開關(guān)控制器
接口: MII
電源電壓: 1.8V,2.5V,3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-PQFP(10x10)
包裝: 托盤
Micrel, Inc.
KSZ8873MLL/FLL/RLL
September 20, 2013
64
Revision 1.6
Register 19
(5) (0x13): Port 1 Control 3
Register 35 (0x23): Port 2 Control 3
Register 51 (0x33): Port 3 Control 3
Bit
Name
R/W
Description
Default
7-0
Default Tag
[15:8]
R/W
Port’s default tag, containing
7-5 : User priority bits
4 : CFI bit
3-0 : VID[11:8]
0x00
Register 20
(5) (0x14): Port 1 Control 4
Register 36 (0x24): Port 2 Control 4
Register 52 (0x34): Port 3 Control 4
Bit
Name
R/W
Description
Default
7-0
Default Tag
[7:0]
R/W
Port’s default tag, containing
7-0
: VID[7:0]
0x01
Note:
5.
Registers 19 and 20 (and those corresponding to other ports) serve two purposes:
a.
Associated with the ingress untagged packets, and used for egress tagging.
b.
Default VID for the ingress untagged or null-VID-tagged packets, and used for address lookup.
Register 21 (0x15): Port 1 Control 5
Register 37 (0x25): Port 2 Control 5
Register 53 (0x35): Port 3 Control 5
Bit
Name
R/W
Description
Default
7
Port 3 MII Mode
Selection
R/W
=1, Port 3 MII MAC mode
=0, Port 3 MII PHY mode
Note:
Bit 7 is reserved in the port 1 and port 2 of the port register control
5. But request to set the register 21 port 1 control 5 bit [7] = ‘1’ for
better EMI, because this bit 7 of the register 21 is for port 1 MII of
the MML part. In the MLL/FLL/RLL parts, setting this bit will disable
the unused internal 25MHz clock for the unused port 1 MII PHY
mode circuits.
Inversion of
power strapped value
of SMRXDV3.
6
Self-Address
Filtering Enable
MACA1
(not for 0x35)
R/W
=1, Enable port 1 self-address filtering MACA1
=0, Disable
0
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