參數(shù)資料
型號(hào)： KSZ8863RLLI
廠商： Micrel Inc
文件頁(yè)數(shù)： 68/106頁(yè)
文件大?。?/td> 0K
描述： IC ETHERNET SWITCH 3PORT 48-LQFP
標(biāo)準(zhǔn)包裝： 250
控制器類型： 以太網(wǎng)開關(guān)控制器
接口： MII
電源電壓： 1.8V，2.5V，3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤
配用： 576-3868-ND - BOARD EVALUATION FOR KSZ8863RLL
其它名稱： 576-3752
PIC16C72 Series
1998 Microchip Technology Inc.
Preliminary
DS39016A-page 63
10.4
Power-On Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.5V - 2.1V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will eliminate
external RC components usually needed to create a
Power-on Reset. A maximum rise time for VDD is spec-
ied. See Electrical Specications for details. For a
slow rise time, see Figure 10-6.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature,...) must be met to ensure oper-
ation. If these conditions are not met, the device must
be held in reset until the operating conditions are met.
Brown-out Reset may be used to meet the startup con-
ditions.
FIGURE 10-6: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
10.5
Power-up Timer (PWRT)
The Power-up Timer provides a xed 72 ms nominal
time-out on power-up only, from the POR. The Power-
up Timer operates on an internal RC oscillator. The
chip is kept in reset as long as the PWRT is active. The
PWRT’s time delay allows VDD to rise to an acceptable
level. A conguration bit is provided to enable/disable
the PWRT.
The power-up time delay will vary from chip to chip due
to VDD, temperature, and process variation. See DC
parameters for details.
10.6
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal oscil-
lator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
10.7
Brown-Out Reset (BOR)
A conguration bit, BODEN, can disable (if clear/pro-
grammed) or enable (if set) the Brown-out Reset cir-
cuitry. If VDD falls below 4.0V (3.8V - 4.2V range) for
greater than parameter #35, the brown-out situation will
reset the chip. A reset may not occur if VDD falls below
4.0V for less than parameter #35. The chip will remain
in Brown-out Reset until VDD rises above BVDD. The
Power-up Timer will now be invoked and will keep the
chip in RESET an additional 72 ms. If VDD drops below
BVDD while the Power-up Timer is running, the chip will
go back into a Brown-out Reset and the Power-up
Timer will be initialized. Once VDD rises above BVDD,
the Power-up Timer will execute a 72 ms time delay.
The Power-up Timer should always be enabled when
Brown-out Reset is enabled.
Note 1: External Power-on Reset circuit is
required only if VDD power-up slope is too
slow. The diode D helps discharge the
capacitor quickly when VDD powers down.
2: R < 40 k
is recommended to make sure
that voltage drop across R does not violate
the device’s electrical specication.
3: R1 = 100
to 1 k will limit any current
owing into MCLR from external capacitor
C in the event of MCLR/VPP pin break-
down due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS).
C
R1
R
D
VDD
MCLR
PIC16CXXX
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