FIGURE 13-13: I2
參數(shù)資料
型號(hào)： KSZ8863RLLI
廠商： Micrel Inc
文件頁(yè)數(shù)： 101/106頁(yè)
文件大?。?/td> 0K
描述： IC ETHERNET SWITCH 3PORT 48-LQFP
標(biāo)準(zhǔn)包裝： 250
控制器類型： 以太網(wǎng)開關(guān)控制器
接口： MII
電源電壓： 1.8V，2.5V，3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤
配用： 576-3868-ND - BOARD EVALUATION FOR KSZ8863RLL
其它名稱： 576-3752
PIC16C72 Series
1998 Microchip Technology Inc.
Preliminary
DS39016A-page 93
FIGURE 13-13: I2C BUS DATA TIMING
TABLE 13-11
I2C BUS DATA REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Max
Units
Conditions
100
THIGH
Clock high time
100 kHz mode
4.0
—
s
Device must operate at a mini-
mum of 1.5 MHz
400 kHz mode
0.6
—
s
Device must operate at a mini-
mum of 10 MHz
SSP Module
1.5TCY
—
101
TLOW
Clock low time
100 kHz mode
4.7
—
s
Device must operate at a mini-
mum of 1.5 MHz
400 kHz mode
1.3
—
s
Device must operate at a mini-
mum of 10 MHz
SSP Module
1.5TCY
—
102
TR
SDA and SCL rise
time
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1Cb
300
ns
Cb is specied to be from
10 to 400 pF
103
TF
SDA and SCL fall time 100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1Cb
300
ns
Cb is specied to be from
10 to 400 pF
90
TSU:STA
START condition
setup time
100 kHz mode
4.7
—
s
Only relevant for repeated
START condition
400 kHz mode
0.6
—
s
91
THD:STA
START condition hold
time
100 kHz mode
4.0
—
s
After this period the rst clock
pulse is generated
400 kHz mode
0.6
—
s
106
THD:DAT
Data input hold time
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
s
107
TSU:DAT
Data input setup time
100 kHz mode
250
—
ns
Note 2
400 kHz mode
100
—
ns
92
TSU:STO
STOP condition setup
time
100 kHz mode
4.7
—
s
400 kHz mode
0.6
—
s
109
TAA
Output valid from
clock
100 kHz mode
—
3500
ns
Note 1
400 kHz mode
—
ns
110
TBUF
Bus free time
100 kHz mode
4.7
—
s
Time the bus must be free
before a new transmission can
start
400 kHz mode
1.3
—
s
Cb
Bus capacitive loading
—
400
pF
Note 1:
As a transmitter, the device must provide this internal minimum delay time to bridge the undened region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
Note 2:
A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz)S I2C-bus system, but the requirement
tsu;DAT
≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specication) before the SCL line is
released.
Note: Refer to Figure 13-1 for load conditions
90
91
92
100
101
103
106
107
109
110
102
SCL
SDA
In
SDA
Out
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