參數(shù)資料
型號(hào): KSZ8851-16MLLI
廠商: Micrel Inc
文件頁數(shù): 69/84頁
文件大小: 0K
描述: IC MAC CTLR 1PORT W/BUS 48-TQFP
標(biāo)準(zhǔn)包裝: 250
控制器類型: 以太網(wǎng)控制器,MAC/PHY
接口: 總線
電源電壓: 1.8V,2.5V,3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 托盤
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
其它名稱: 576-3505
2002 Microchip Technology Inc.
DS30325B-page 69
PIC16F7X
10.0
UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Com-
munications Interface or SCI.) The USART can be con-
figured as a full duplex asynchronous system that can
communicate with peripheral devices, such as CRT ter-
minals and personal computers, or it can be configured
as a half duplex synchronous system that can commu-
nicate with peripheral devices, such as A/D or D/A inte-
grated circuits, serial EEPROMs, etc.
The USART can be configured in the following modes:
Asynchronous (full duplex)
Synchronous - Master (half duplex)
Synchronous - Slave (half duplex)
Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to
be set in order to configure pins RC6/TX/CK and
RC7/RX/DT as the Universal Synchronous Asynchro-
nous Receiver Transmitter.
REGISTER 10-1:
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0
U-0
R/W-0
R-1
R/W-0
CSRC
TX9
TXEN
SYNC
BRGH
TRMT
TX9D
bit 7
bit 0
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1
= Master mode (clock generated internally from BRG)
0
= Slave mode (clock from external source)
bit 6
TX9: 9-bit Transmit Enable bit
1
= Selects 9-bit transmission
0
= Selects 8-bit transmission
bit 5
TXEN: Transmit Enable bit
1
= Transmit enabled
0
= Transmit disabled
Note:
SREN/CREN overrides TXEN in Sync mode.
bit 4
SYNC: USART Mode Select bit
1
= Synchronous mode
0
= Asynchronous mode
bit 3
Unimplemented: Read as '0'
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1
= High speed
0
= Low speed
Synchronous mode:
Unused in this mode
bit 1
TRMT: Transmit Shift Register Status bit
1
= TSR empty
0
= TSR full
bit 0
TX9D: 9th bit of Transmit Data
Can be parity bit
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
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