參數(shù)資料
型號(hào): KSZ8842-PMBL AM
廠商: Micrel Inc
文件頁(yè)數(shù): 29/119頁(yè)
文件大?。?/td> 0K
描述: IC ETHERNET SW 2PORT 100-LFBGA
標(biāo)準(zhǔn)包裝: 260
控制器類型: 以太網(wǎng)開關(guān)控制器
接口: PCI
電源電壓: 3.1 V ~ 3.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LFBGA
供應(yīng)商設(shè)備封裝: 100-LFBGA
包裝: 托盤
產(chǎn)品目錄頁(yè)面: 1081 (CN2011-ZH PDF)
配用: 576-1636-ND - BOARD EVALUATION KSZ8842-PMQL
其它名稱: 576-3348
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)當(dāng)前第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)
Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
17
M9999-100207-1.5
Ball
Number
Ball
Name
Type
Ball Function
defines the start of each phase. The clock maximum frequency is 33MHz.
B4
INTRN
Opd
Interrupt Request. Active Low signal to host CPU to request an interrupt when any one of the
interrupt conditions occurs in the registers. This pin should be pull-up externally.
A4
EECS
Opu
EEPROM Chip Select. This signal is used to select an external EEPROM device
C3
P2LED3
Opd
Port 2 LED Indicator
See the description in ball B5, B6 and A6.
A3
EEEN
Ipd
EEPROM Enable
EEPROM is enabled and connected when this pin is pull-up.
EEPROM is disabled when this pin is pull-down or no connect.
B3
P1LED3
Opd
Port 1 LED indicator
See the description in ball C7, A7 and B7.
B2
EEDO
Opd
EEPROM Data Out:
This pin is connected to DI input of the serial EEPROM.
A2
EESK
Opd
EEPROM Serial Clock:
A 4
s serial output clock to load configuration data from the serial EEPROM.
A1
EEDI
Ipd
EEPROM Data In:
This pin is connected to DO output of the serial EEPROM.
B1
PWRDN
Ipu
Full-chip power-down. Active Low.
C1
RXP1
I/O
Port 1 physical receive (MDI) or transmit (MDIX) signal (+ differential)
C2
RXM1
I/O
Port 1 physical receive (MDI) or transmit (MDIX) signal (– differential)
D1
TXP1
I/O
Port 1 physical transmit (MDI) or receive (MDIX) signal (+ differential)
D2
TXM1
I/O
Port 1 physical transmit (MDI) or receive (MDIX) signal (– differential)
F2
RXM2
I/O
Port 2 physical receive (MDI) or transmit (MDIX)signal (- differential)
F1
RXP2
I/O
Port 2 physical receive(MDI) or transmit (MDIX) signal (+ differential)
G2
TXM2
I/O
Port 2 physical transmit (MDI) or receive (MDIX) signal (- differential)
G1
TXP2
I/O
Port 2 physical transmit (MDI) or receive (MDIX) signal (+ differential)
G3
ISET
O
Set physical transmit output current.
Pull-down this ball with a 3.01K 1% resistor.
H1
X1
I
H2
X2
O
25MHz crystal/oscillator clock connections
Balls (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V tolerant
oscillator and X2 is a no connect.
Note: Clock is
± 50ppm for both crystal and oscillator.
J1
RSTN
Ipu
Hardware Reset, Active Low
RSTN will cause the KSZ8842-PMBL to reset all of its functional blocks. RSTN must be
asserted for a minimum duration of 10 ms.
J2
PAR
O
PCI Parity
Even parity computed for PAD [31:0] and CBE[3:0]N, master drives PAR for address and
write data phase, target drives PAR for read data phase.
K1
FRAMEN
I/O
PCI Cycle Frame
This signal is asserted low to indicate the beginning of the address phase of the bus
transaction and de-asserted before the final transfer of the data phase of the transaction in a
bus master mode. As a target, the device monitors this signal before decoding the address to
check if the current transaction is addressed to it.
相關(guān)PDF資料
PDF描述
V72A28C400BL3 CONVERTER MOD DC/DC 28V 400W
V72A28C400BL2 CONVERTER MOD DC/DC 28V 400W
V72A28C400BL CONVERTER MOD DC/DC 28V 400W
V72A28C400B3 CONVERTER MOD DC/DC 28V 400W
V72A15C400BG3 CONVERTER MOD DC/DC 15V 400W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KSZ8842-PMBL-EVAL 功能描述:以太網(wǎng)開發(fā)工具 2+1 Port 10/100 Ethernet Switch with 32b/33MHz PCI Interface (BGA Version) Eval Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類型:RMII 工作電源電壓:
KSZ8842-PMBL-TR 功能描述:Ethernet Switch 10/100 Base-T/TX PHY PCI Interface 100-LFBGA (9x9) 制造商:microchip technology 系列:- 包裝:剪切帶(CT) 零件狀態(tài):停產(chǎn) 協(xié)議:以太網(wǎng) 功能:開關(guān) 接口:PCI 標(biāo)準(zhǔn):10/100 Base-T/TX PHY 電壓 - 電源:3.1 V ~ 3.5 V 電流 - 電源:122mA 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LFBGA 供應(yīng)商器件封裝:100-LFBGA(9x9) 標(biāo)準(zhǔn)包裝:1
KSZ8842-PMQL 功能描述:以太網(wǎng) IC 2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI bus interface(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8842-PMQL-EVAL 功能描述:以太網(wǎng)開發(fā)工具 KSZ8842-PMQL Evaluation Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類型:RMII 工作電源電壓:
KSZ8842-PMQLI 功能描述:以太網(wǎng) IC 2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI bus interface, Ind Temp (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray