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參數(shù)資料
| 型號： | KSZ8051MLL |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 2/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX PHY 10/T100 3.3V MII 48LQFP |
| 特色產(chǎn)品： | KSZ8051MLL Physical Layer Transceiver KSZ8051/8031/8021 Series |
| 標準包裝： | 250 |
| 類型： | PHY 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | MII |
| 電源電壓： | 1.8V，2.5V，3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 配用： | 576-3864-ND - BOARD EVALUATION FOR KSZ8051MLL |
| 其它名稱： | 576-3731 |
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Micrel, Inc.
KSZ8051MLL
July 2010
10
M9999-071210-1.0
Pin Description – KSZ8051MLL (Continued)
Pin Number
Pin Name
Type
(1)
Pin Function
26
NC
-
No connect
27
RXDV /
CONFIG2
Ipd/O
MII Mode:
MII Receive Data Valid Output /
Config Mode:
The pull-up/pull-down value is latched as CONFIG2 at the
de-assertion of reset. See Strapping Options section for details.
28
RXC /
B-CAST_OFF
Ipd/O
MII Mode:
MII Receive Clock Output
Config Mode:
The pull-up/pull-down value is latched as B-CAST_OFF at the
de-assertion of reset. See Strapping Options section for details.
29
RXER /
ISO
Ipd/O
MII Mode:
MII Receive Error Output /
Config Mode:
The pull-up/pull-down value is latched as ISOLATE at the
de-assertion of reset. See Strapping Options section for details.
30
GND
Gnd
Ground
31
VDD_1.2
P
1.2V core VDD
(power supplied by KSZ8051MLL)
Decouple with 0.1uF capacitor to ground, and join with pin 4 by power trace or plane.
32
INTRP /
NAND_Tree#
Ipu/Opu
Interrupt Output: Programmable Interrupt Output
This pin has a weak pull-up, is open-drain like, and requires an external 1.0K
Ω
pull-up resistor.
Config Mode:
The pull-up/pull-down value is latched as NAND Tree# at the
de-assertion of reset. See Strapping Options section for details.
33
TXC
I/O
MII Mode:
MII Transmit Clock Output
MII Back-to-Back Mode:
MII Transmit Clock Input
34
TXEN
I
MII Mode:
MII Transmit Enable Input
35
TXD0
I
MII Mode:
MII Transmit Data Input[0]
(3)
36
TXD1
I
MII Mode:
MII Transmit Data Input[1]
(3)
37
GND
Gnd
Ground
38
TXD2
I
MII Mode:
MII Transmit Data Input[2]
(3)
39
TXD3
I
MII Mode:
MII Transmit Data Input[3]
(3)
40
COL /
CONFIG0
Ipd/O
MII Mode:
MII Collision Detect Output /
Config Mode:
The pull-up/pull-down value is latched as CONFIG0 at the
de-assertion of reset. See Strapping Options section for details.
41
CRS /
CONFIG1
Ipd/O
MII Mode:
MII Carrier Sense Output /
Config Mode:
The pull-up/pull-down value is latched as CONFIG1 at the
de-assertion of reset. See Strapping Options section for details.
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| KSZ8051MLL TR | 功能描述:以太網(wǎng) IC 3.3V, 10Base-T/100Base-TX Physical Layer Transceiver w/ MII Support (48-LQFP) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8051MLL-EVAL | 功能描述:以太網(wǎng)開發(fā)工具 3.3V, 10Base-T/100Base-TX Physical Layer Transceiver w/ MII Support (48-LQFP) - Evaluation Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
| KSZ8051MLLI | 功能描述:以太網(wǎng) IC 3.3V, 10Base-T/100Base-TX Physical Layer Transceiver w/ MII Support (48-LQFP, Industrial Grade) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8051MLLI TR | 功能描述:以太網(wǎng) IC 3.3V, 10Base-T/100Base-TX Physical Layer Transceiver w/ MII Support (48-LQFP, Industrial Grade) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8051MLLI-TR | 功能描述:1/1 Transceiver Full MII 48-LQFP (7x7) 制造商:microchip technology 系列:- 包裝:剪切帶（CT） 零件狀態(tài):過期 類型:收發(fā)器 協(xié)議:MII 驅(qū)動器/接收器數(shù):1/1 雙工:全 接收器滯后:- 數(shù)據(jù)速率:- 電壓 - 電源:1.8V，2.5V，3.3V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商器件封裝:48-LQFP（7x7） 標準包裝:1 |
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