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參數(shù)資料
| 型號： | KS9241B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | CD-ROM Decoder(光盤驅(qū)動器解碼器) |
| 中文描述： | 的CD - ROM解碼器（光盤驅(qū)動器解碼器） |
| 文件頁數(shù)： | 32/37頁 |
| 文件大?。?/td> | 211K |
| 代理商： | KS9241B |
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KS9241B
CD-ROM DECODER
32
ERACEN (Erasure Correction Enable):
When data bit is
“
1
”
, the Erasure correction is enabled after the Erasure flag data read from RAM is enabled.
When this data bit is
“
0
”
, the Erasure flag is always considered as
“
1
”
.
BUFEN (Buffering Enable):
When the data bit is
“
1
”
, the buffering is enabled and the decoding block start pointer of DBSPL /DBSPH is
renewed.
QCOEN (Q Code Correction Enable):
When the data is
“
1
”
, the error correction for Q code is enabled.
PCOEN (P Code Correction Enable):
When the data is
“
1
”
, the error correction for P code is enabled.
CONT2 (Control2) register
GSYEN (Generated Sync Enable):
When the data bit is
“
1
”
, the internal sync which is generated by word counter is valid.
1 word is 2 bytes and 1 block is 2352 bytes. Therefore the word counter is enabled to make 1 block period to
gather 1176th syncs.
DSYEN (Detected Sync Enable):
When the data bit is
“
1
”
, it makes the sync, which is detected from the applied input serial data vaild.
DESCEN (Descrambling Enable):
When the data bit is
“
1
”
, Descrambling is available.
CDWEN (Corrected Data Write Enable):
When the data bit is
“
1
”
, it makes available writing of the data, which is through error correction into RAM.
MODSEL (Form Select):
When the data bit is
“
0
”
, the Decoder Mode is established through mode 1, and it is established through mode
2, when the bit is
“
1
”
.
FRMSEL (Form Select):
This flag is valid only when AUTCEN of CONT1 register is
“
0
”
and MODSEL of CONT2 register is
“
1
”
. Besides
it indicates Form 1 when the bit is
“
0
”
and Form 2 when the bit is
“
1
”
.
MODCHK (Mode Check):
When the bit is
“
1
”
, the error correction can be performed only when the mode of MODSEL and mode byte of
the header before error correction coincide.
When the bit is
“
0
”
, the error correction performance is affected by the mode of MODSEL only.
SHREN (Subheader Read Enable):
When the data bit is
“
0
”
, it enables to read the header, and when the bit is
“
0
”
, reading the subheader is
enabled.
RESET Register
The chip reset is performed after writing into this register.
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