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參數(shù)資料
| 型號： | KS9241B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | CD-ROM Decoder(光盤驅(qū)動器解碼器) |
| 中文描述： | 的CD - ROM解碼器（光盤驅(qū)動器解碼器） |
| 文件頁數(shù)： | 25/37頁 |
| 文件大小： | 211K |
| 代理商： | KS9241B |
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CD-ROM DECODER
KS9241B
25
If host reads data from FIFO when the first data is registered into FIFO, the output data will be invalid and in this
case, /DTOPR bit of ISTATE register will be
“
0
”
and /DREN pin will
“
L
”
only after reading is finished at host. Data
transmission is finished when host reads data so much as the byte number established by micom. The moment
host starts to read the last byte, /DTUOP bit of ISTATE register becomes
“
1
”
, and /DREN bit becomes
“
H
”
. While
host is reading the last byte, /DTE bit becomes
“
L
”
. During the period of finishing the reading to writing into
DTEACK register, /DTINT bit of ISTATE register becomes
“
0
”
. At this moment, if the DTIEN bit of ICONT is
“
1
”
the
/INT pin becomes
“
L
”
. /WAIT signal output occurs at /WAIT pin when /SEL pin is
“
H
”
. Besides, host starts to read
data from FIFO for data transmission then, and if no data is written in FIFO, the /WAIT pin becomes
“
L
”
. On
condition that /SEL pin is
“
L
”
, data demanding signal is generated at /WAIT pin. The /WAIT pin is valid only which
host is reading data. The signal waveform of the following picture explains the case of transmission of 4 byte from
1*st address.
(ii) Wait Operation
(Wait Operation Timing)
Figure 19.
NOTE:
Condition : /HCS =
“
L
”
,/ CMD =
“
L
”
, /HWR =
“
L
”
/MCS =
“
L
”
, MRS =
“
H
”
, /MRD =
“
H
”
, Address Decoder =
“
0
”
If /DTWT bit of ICONT register is
“
0
”
, wait operation is started during status byte transmission. On condition that
the writing into DTSTR register is performed and finished by host, the /DTUOP bit of ISTATE register becomes
“
0
”
.
However, if status was then being transmitted, /DTOPR bit of ISTATE register becomes
“
0
”
and /DREN bit
becomes
“
L
”
, only when /STOPR bit of ISTATE register is
“
1
”
after status transmission is finished. After that, the
operation is as follows:
(Wait Operation Timming) /STWT =
“
0
”
)
(/DTWT =
“
0
”
) AD=6
/MWR
/STUOP
/STOPR
/SREN
/DTUOP
/DTOPR
/DREN
/CMD
/HRD
/HRD
/HD7-0.HDE
6
d1
d2
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