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參數資料
| 型號： | KS9241B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | CD-ROM Decoder(光盤驅動器解碼器) |
| 中文描述： | 的CD - ROM解碼器（光盤驅動器解碼器） |
| 文件頁數： | 29/37頁 |
| 文件大?。?/td> | 211K |
| 代理商： | KS9241B |
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CD-ROM DECODER
KS9241B
29
In terms of reading subheader, from 16th to 19th byte are read on condition that the first sync byte is 0th byte.
However, on condition that error flag is set, the data is replaced from 20th to 23th byte. In case of corresponding 2
bytes with error flag which is set, 20th to 23th byte are read.
DBSPL (Decoding Block Start Pointer Low) Register
DBSPH (Decoding Block Start Pointer High) Register:
They indicate the forwarding address of the block which is under decoding, and DBSPL register indicates LSB 8
bits and DBSPH register indicates MSB 8 bits. Further more, the forwarding address means the address of
header
’
s first byte. Since this register is in control of micom , the block can be changed by micom.
BPTRL (Buffering Pointer Low ) Register/ BPTRL (Buffering Pointer High ) Register
It is a counter about the address which are applied from DSP for CDP system and buffered at RAM.
STATE 1 register
NOERR (No Error):
If
“
1
”
, the result of 32 bit CRC indicates no error in the block.
NOGSY (No Generated Sync):
If
“
1
”
, the sync detected by input data is different from the internal sync by word counter.
Then, the decoder is synchronized by the detected sync.
NODSY (No Detected Sync):
If
“
1
”
, the sync by input data is not detected at the position of the internal sync by word counter.
Then, the decoder is synchronized by generated sync.
LNGBLK (Long Block):
If
“
1
”
, the sync from input data at the position of internal sync is not detected on condition that GSYEN of
CONT 2 register and DSYEN is
“
1
”
.
This result indicates that the 1 indicates that the 1 block duration time gets longer
SRTWD (Short Word):
If
“
1
”
, it indicates that one word period is shorter than 192 clock of XIN bit signal, and then the decoder
operation is stopped.
SRTBLK (Short Block):
If
“
1
”
, the detected sync from input data is different from the internal sync, on condition that GSYEN is
“
1
”
and
DSYEN is
“
0
”
in CONT 2 register.
EFIBLK (Erasure Flag In Block):
If
“
1
”
, it indicates that there is more than one error flag which is set in block. Here, the block is from header to
EDC parity.
UEIBLK(Uncorrectable Errors In Block):
If
“
1
”
, it indicates that more than one codeword of uncorrectable error is found. Here, the block is from header
to ECC parity.
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