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參數(shù)資料
| 型號(hào)： | KS7308 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Frequency Conversion Memory(頻率轉(zhuǎn)換存儲(chǔ)器) |
| 中文描述： | 變頻內(nèi)存（頻率轉(zhuǎn)換存儲(chǔ)器） |
| 文件頁(yè)數(shù)： | 9/13頁(yè) |
| 文件大?。?/td> | 64K |
| 代理商： | KS7308 |
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KS7308 FCM
2. SIO REGISTER
[Register diagram]
SMOS resister
Read start address register (2 Byte)
Defines read start position in the bank memory.
UD = 0 : Ciybter increment UD = 1 : Counter decrement
Write start address register (2 Byte)
Defines write start position in the bank memory
HD control register
Control to start read address counter incrementation from rising edge of HD.
RE = 0, WE = 1 : Write enable (Write to register)
RE = 1, WE = 0 : Read enable (Read from counter outupt without UD bit)
RE = 0, WE = 0 : No operation RE = 1, WE = 1 : Prohibited
0
0
0
0
RE
WE
0
0
MSB
(lst Byte)
LSB
0
0
0
0
UD
A9
A8
MSB
(2nd Byte)
LSB
0
A7
A6
A5
A4
A2
A1
A0
MSB
(3rd Byte)
LSB
A3
group address
0
0
0
0
0
A9
A8
MSB
(4th Byte)
LSB
0
A7
A6
A5
A4
A2
A1
A0
MSB
(5th Byte)
LSB
A3
D7
D6
D5
D4
D2
D1
D0
MSB
(6th Byte)
LSB
D3
1
1
1
0
1
0
P
MSB
(7th Byte)
LSB
0
P : Even parity
Stop Byte
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