Preliminary
DSP for Digital Answering phone with FLASH interface
KS16121
PIN DESCRIPTION
Pin Name
Pin No.
DESCRIPTION
HD[7:0]
HWB
HRB
HLB
HREQB
DATF
BCLK
FSYNC
APD1
DX1
DR1
APD2
DX2
DR2
ADD[15:4]
ROEB
WEB/ADD3
ALE/ADD2
CLE/ADD1
REB/ADD0
CEB1
CEB2
CEB3
CEB4
RBB
DQ[7:0]
XI
XO
RESETB
PDNB
V
DD
V
SS
Host data bus for host instructions and status words from KS16121. Pull-up.
Host Write Strobe. A low to high transition loads an instruction into the KS16121.
Host Read Strobe. The KS16121 writes a status word to the host data bus when HRB is Low.
Lower Byte Select. 16-bit command and status words are written or read, 8 bits at a time
When low, this signal indicates that lower byte is selected.
Host Read Request. Indicates that a status word is ready for the host to read. Active Low.
It goes inactive when the higher byte of a status word is read by the host.
Not used.
PCM Data Receive/Transmit Bit Clock for Codec 1 and 2. ( 2.048MHz clock )
PCM Data Receive/Transmit Frame Sync Clock for Codec 1 and 2.
Codec 1 Inactive Flag. When set, indicates the codec is not used and may be powered down.
PCM data Transmit pin to Codec 1 . Serial data output from KS16121 to codec.
PCM Data Receive pin from Codec 1. Serial data output from codec to KS16121. Pull-up.
Codec 2 Inactive Flag. When set, indicates the codec is not used and may be powered down.
PCM data transmit pin to Codec 2. Serial data output from KS16121 to codec.
PCM data Receive pin from Codec 2. Serial data output from codec to KS16121. Pull-up.
Address Bus for ROM/EPROM.
ROM/EPROM Output Enable. Active Low.
Flash Memory Write Enable. Active Low. ROM / EPROM Address bit 3
Flash Memory Address Latch Enable. Active High. ROM / EPROM Address bit 2
Flash Memory Command Latch Enable. Active High. ROM / EPROM Address bit 1.
Flash Memory Read Enable. Active Low. ROM / EPROM Address bit 0.
Chip Enable for first Flash Memory. Active Low.
Chip Enable for second Flash Memory. Active Low.
Chip Enable for third Flash Memory. Active Low.
Chip Enable for fourth Flash Memory. Active Low.
Flash memory Ready / Busy signal. If low, flash memory is busy.
Data bus for flash memory and ROM / EPROM. Pull -up
Crystal Input Pin. 24.576MHz
Crystal Output Pin.
System Reset. Active Low.
System Power Down. Active Low.
Chip Power Supply ( 1,17,33,41,52, 62,72,77 )
64 - 71
60
59
58
61
57
51
54
49
47
55
50
48
56
75-76,79-80
3 -10
74
11
12
13
20
19
16
15
14
21
22-29
39
40
46
45
Type
I / O
I
I
I
O
O
O
O
O
O
I
O
O
I
O
O
O
O
O
O
O
O
O
O
I
I / O
I
O
I
I
I
I
Chip Ground. ( 2,18,34,42,53, 63,73,78 )