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參數(shù)資料
| 型號： | KS16121 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DSP for Digital Answering Phone(用于數(shù)字應答電話的DSP) |
| 中文描述： | DSP的數(shù)字應答電話（用于數(shù)字應答電話的數(shù)字信號處理器） |
| 文件頁數(shù)： | 20/30頁 |
| 文件大?。?/td> | 147K |
| 代理商： | KS16121 |
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Preliminary
DSP for Digital Answering phone with FLASH interface
KS16121
HARDWARE INTERFACE
The KS16121 contains a DSP core, program ROM, data SRAM and interface logic.
The interface logic consists of Memory, Codec and Host interfaces.
CLOCKING
The KS16121 has an on-chip oscillator. It requires a crystal with fc = 24.576 MHz.
RESET
When power - up the system first after power failure , the KS16121 must be reset with a pulse at the
RESET pin for a minimum duration of 100 nsec, in order to clear internal registers, set operating parameters
to their default values, and initialize the DSP software program.
A reset is strongly recommended after a power failure.
HOST INTERFACE
The host communicates with the KS16121 through the host interface which is an 8-bit parallel interface
with separate read / write strobes, as shown in Figure 2.
The host writes instructions and reads status words via the 8-bit bi-directional port in two successive
accesses. Two bytes of a 16-bit instruction / status word are distinguished with HLB input pin. For proper
communication, the lower byte ( with HLB low ) should be accessed first , followed by the higher byte ( with
HLB high ).
The KS16121 executes the instruction after the higher byte is written by the host. When a status word is
ready for the host, the KS16121 pulls the HREQB output low, which may be used as a host interrupt. The
host then reads the lower byte of the status, followed by the higher byte at which time the KS16121 sets
HREQB high.
POUT
INT
HLB
HD[7:0]
HRB
HWB
HREQB
HLB
HOST
KS16121
Figure 2. Host Interface for KS16121
RD
WR
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