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參數(shù)資料
| 型號： | KS0794 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 160 COM / 160 SEG DRIVER FOR STN LCD |
| 中文描述： | 160的COM / 160賽格驅(qū)動STN液晶顯示器 |
| 文件頁數(shù)： | 14/31頁 |
| 文件大?。?/td> | 268K |
| 代理商： | KS0794 |
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160 COM / SEG DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.1 KS0794
14
Common Mode (Continued)
DISPOFFB
Control input pin for output deselect level
. The input signal is level-shifted from logic voltage level to LC drive voltage
level, and controls LC drive circuit.
. When set to V
SS
level “L”, the LC drive output pins (Y
1
- Y
160
) are set to level
V
SS
.
. While set to “L”, the contents of the shift resister are reset not reading data.
When the DISPOFFB function is canceled, the driver outputs deselect
Level (V
12
or V
43
), and the shift data is reading on the falling edge of the LP.
That time, if DISPOFFB removal time can not keep regulation what is shown
AC characteristics (page 25), the shift data is not reading correctly.
AC signal input for LC driving waveform
. The input signal is level-shifted from logic voltage level to LC drive voltage
level, and controls LC drive circuit.
. Normally, input a frame inversion signal.
. The LC driver output pin’s output voltage level can be set using the shift
register output signal and the FR signal.
Table of truth values are shown in table 4.
Mode selection pin
. When set to V
SS
level “L”, Single mode operation is selected, when set to
V
DD
level “H”, Dual mode operation is selected.
Dual Mode data input pin
. According to the data shift direction of the data shift register, data can be
input starting from the 81
st
bit.
When the chip is used as Dual mode, DI
7
will be pull-down.
When the chip is used as Single mode, DI
7
won’t be pull-down.
Segment mode / Common mode selection pin
. When set to V
SS
level ‘L”, common mode is set.
Not used
. Connect DI
0 -
DI
6
to V
SS
or V
DD
. Avoiding floating.
Not used
. XCK is pull-down in common mode, so connect to V
SS
or open.
LC driver output pins
. Corresponding directly to each bit of the shift register, one level (V0, V12,
V43, or VSS) is selected and output.
Table of truth values are shown in table 4.
FR
MD
DI
7
S/C
DI
0
– DI
6
XCK
Y
1
– Y
160
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