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參數資料
| 型號： | KS0794 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 160 COM / 160 SEG DRIVER FOR STN LCD |
| 中文描述： | 160的COM / 160賽格驅動STN液晶顯示器 |
| 文件頁數： | 12/31頁 |
| 文件大小： | 268K |
| 代理商： | KS0794 |
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160 COM / SEG DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.1 KS0794
12
Segment Mode (Continued)
FR
AC signal input for LC driving waveform
. The input signal is level-shifted from logic voltage level to LC drive voltage
level, and controls LC drive circuit.
. Normally, inputs a frame inversion signal.
. The LC driver output pin’s output voltage level can be set using the line
latch output signal and the FR signal.
Table of truth values is shown in table 4.
Mode selection pin
. When set to V
SS
level “L”, 4-bit parallel input mode is set.
. When set to V
DD
level “H”, 8-bit parallel input mode is set.
. The relationship between the display data and driver output pins is shown
in table 5.
Segment mode / common mode selection pin
. When set to V
DD
level ‘H”, segment mode is set.
Input / output pin for chip selection
. When L/R input is at V
SS
level ‘L”, EIO
1
is set for output, and EIO
2
is set for
input.
. When L/R input is at V
DD
level ‘H”, EIO
1
is set for input, and EIO
2
is set for
output.
. During output. set to “H” while LP*XCLKB is ‘H” and after 160-bits of data
have been read, set to “L” for one cycle (from falling edge to falling edge of
XCK), after which it returns to “H”.
. During input, after the LP signal is input, the chip is selected while EI is set
to “L”. After 160-bits of data have been read, the chip is deselected.
LC driver output pins
. Corresponding directly to each bit of the data latch, one level (V
0
, V
12
, V
43
,
or V
SS
) is selected and output.
Table of truth values are shown in table 4.
MD
S/C
EIO
1
EIO
2
Y
1
– Y
160
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