參數(shù)資料
型號(hào)： KMSC7118VM1200
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 20/60頁(yè)
文件大小： 0K
描述： DSP 16BIT W/DDR CTRLR 400-MAPBGA
標(biāo)準(zhǔn)包裝： 2
系列： StarCore
類型： 定點(diǎn)
接口： 主機(jī)接口，I²C，UART
時(shí)鐘速率： 300MHz
非易失內(nèi)存： ROM（8 kB）
芯片上RAM： 464kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 400-LFBGA
供應(yīng)商設(shè)備封裝： 400-MAPBGA（17x17）
包裝： 托盤
Electrical Characteristics
MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7
Freescale Semiconductor
27
Figure 6 shows the DDR DRAM output timing diagram.
209
Dn/DQMn output setup with respect to DQSn3
tDDKHDS,
tDDKLDS
0.25
× tCK – 750
—
ps
210
Dn/DQMn output hold with respect to DQSn3
tDDKHDX,
tDDKLDX
0.25
× tCK – 750
—
ps
211
DQSn preamble start4
tDDKHMP
–0.25
× tCK
—ps
212
DQSn epilogue end5
tDDKHME
–600
600
ps
Notes:
1.
All CK/CK referenced measurements are made from the crossing of the two signals ±0.1 V.
2.
tDDKHMH can be modified through the TCFG2[WRDD] DQSS override bits. The DRAM requires that the first write data strobe
arrives 75–125% of a DRAM cycle after the write command is issued. Any skew between DQSn and CK must be considered
when trying to achieve this 75%–125% goal. The TCFG2[WRDD] bits can be used to shift DQSn by 1/4 DRAM cycle
increments. The skew in this case refers to an internal skew existing at the signal connections. By default, the CK/CK crossing
occurs in the middle of the control signal (An/RAS/CAS/WE/CKE) tenure. Setting TCFG2[ACSM] bit shifts the control signal
assertion 1/2 DRAM cycle earlier than the default timing. This means that the signal is asserted no earlier than 600 ps before
the CK/CK crossing and no later than 600 ps after the crossing time; the device uses 1200 ps of the skew budget (the interval
from –600 to +600 ps). Timing is verified by referencing the falling edge of CK. See Chapter 10 of the MSC711x Reference
Manual for details.
3.
Determined by maximum possible skew between a data strobe (DQS) and any corresponding bit of data. The data strobe
should be centered inside of the data eye.
4.
Please note that this spec is in reference to the DQSn first rising edge. It could also be referenced from CK(r), but due to
programmable delay of the write strobes (TCFG2[WRDD]), there pre-amble may be extended for a full DRAM cycle. For this
reason, we reference from DQSn.
5.
All outputs are referenced to the rising edge of CK. Note that this is essentially the CK/DQSn skew in spec 208. In addition
there is no real “maximum” time for the epilogue end. JEDEC does not require this is as a device limitation, but simply for the
chip to guarantee fast enough write-to-read turn-around times. This is already guaranteed by the memory controller operation.
Figure 6. DDR DRAM Output Timing Diagram
Table 18. DDR DRAM Output AC Timing (continued)
No.
Parameter
Symbol
Min
Max
Unit
An
Dn
DQSn
CK
D1
D0
Write A0
NOOP
RAS
CAS
WE
CKE
200
208
209
212
210
211
206
204
207
205
DQMn
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