參數(shù)資料
型號(hào)： KMPC8560VTAQFB
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 7/36頁(yè)
文件大?。?/td> 0K
描述： IC MPU POWERQUICC III 783-FCPBGA
標(biāo)準(zhǔn)包裝： 2
系列： MPC85xx
處理器類(lèi)型： 32-位 MPC85xx PowerQUICC III
速度： 1.0GHz
電壓： 1.3V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 784-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤(pán)
MOTOROLA
MPC8560 PowerQUICC III
15
Integrated Communications Processor Product Brief
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
DDR SDRAM Controller
memory. It also provides a flexible switch-type structure for core and I/O-initiated transactions to be routed
or dispatched to target modules on the device.
3.5
DDR SDRAM Controller
The MPC8560 supports DDR-I SDRAM that operates at up to 166 MHz (333-MHz data rate). The memory
interface controls main memory accesses and provides for a maximum of 3.5 Gbytes of main memory. The
memory controller can be configured to support the various memory sizes through software initialization of
on-chip configuration registers.
The MPC8560 supports a variety of SDRAM configurations. SDRAM banks can be built using DIMMs or
directly-attached memory devices. Fifteen multiplexed address signals provide for device densities of
64 Mbits, 128 Mbits, 256 Mbits, and 512 Mbits, and 1 Gbit. Four chip select signals support up to four
banks of memory. The MPC8560 supports bank sizes from 64 Mbytes to 1 Gbyte. Nine-column address
strobes (MDM[0:8]) are used to provide byte selection for memory bank writes.
The MPC8560 can be configured to retain the currently active SDRAM page for pipelined burst accesses.
Page mode support of up to 16 simultaneously open pages can dramatically reduce access latencies for page
hits. Depending on the memory system design and timing parameters, using page mode can save 3 to 4 clock
cycles from subsequent burst accesses that hit in an active page.
The MPC8560 supports ECC for system memory. Using ECC, the MPC8560 detects and corrects all
single-bit errors and detects all double-bit errors and all errors within a nibble.
The MPC8560 can invoke a level of system power management by asserting the MCKE SDRAM signal
on-the-fly to put the memory into a low-power sleep mode.
3.6
Programmable Interrupt Controller (PIC)
The programmable interrupt controller (PIC) implements the necessary functions to provide a flexible
solution for a general-purpose interrupt control. The interrupt controller unit implements the logic and
programming structures of the OpenPIC architecture. The MPC8560 interrupt controller unit supports its
processor core and provides for 12 external interrupts (with fully nested interrupt delivery), 4 message
interrupts, internal-logic driven interrupts, and 4 global high resolution timers. Up to 16 programmable
interrupt priority levels are supported.
The interrupt controller unit can be bypassed to allow use of an external interrupt controller. Inter-processor
interrupt (IPI) communication is supported through the external interrupt and core reset signals of different
processor cores on the same device. The four IPIs are only used for self-interrupt in a single-core device
such as the MPC8560.
3.7
I2C Controller
The inter-IC (IIC or I2C) bus is a two-wire, bidirectional serial bus that provides a simple and efficient
method of data exchange between devices. The synchronous, multiple master bus of the I2C allows the
MPC8560 to exchange data with other I2C devices, such as microcontrollers, EEPROMs, real-time clock
devices, A/D converters, and LCDs. The two-wire bus (serial data SDA and serial clock SCL) minimizes
the interconnections between devices. The synchronous, multiple master bus of the I2C allows the
connection of additional devices to the bus for expansion and system development.
The I2C controller is a true multiple master bus; it includes collision detection and arbitration that prevents
data corruption if two or more masters attempt to control the bus simultaneously. This feature allows for
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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