參數(shù)資料
型號： KMPC8560VTAQFB
廠商： Freescale Semiconductor
文件頁數(shù)： 28/36頁
文件大?。?/td> 0K
描述： IC MPU POWERQUICC III 783-FCPBGA
標準包裝： 2
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.0GHz
電壓： 1.3V
安裝類型： 表面貼裝
封裝/外殼： 784-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
34
MPC8560 PowerQUICC III
MOTOROLA
Integrated Communications Processor Product Brief
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MPC8560 Configurations
6.5
MPC8560 Configurations
The MPC8560 offers flexibility in configuring the device for specific applications. The functions mentioned
in the above sections are all available in the device, but not all of them can be used at the same time. This
does not imply that the device is not fully activated in any given implementation. The CPM architecture has
the advantage of using common hardware resources for many different protocols and applications. Two
factors limit the functionality in any given system: pinout and performance.
6.6
Pin Configurations
To maximize the efficiency of device pins, some pins have multiple functions. In some cases choosing a
function may preclude the use of another function.
6.7
Communications Performance
The CPM is designed to handle an aggregate of 1 Gbps on the communications channels running at
333 MHz. Performance depends on a number of factors:
Channel rate versus CPM clock frequency for adequate polling of communications channels for
service
Channel rate and protocol versus CPM clock frequency for CP protocol handling
Channel rate and protocol versus bus bandwidth
Channel rate and protocol versus system core clock for adequate protocol handling
The second item above is addressed in this section—the CP’s ability to handle high bit-rate protocols. Slow
bit-rate protocols do not significantly affect those numbers.
Table 2 shows the peak CPM performance of various protocols under the assumption that only one of those
protocols is running at a given time. The ATM numbers shown also assume that the local bus is used
exclusively by the CPM, and enough bandwidth on the DDR memory system is available for the CPM
(implying that other resources, such as the PCI-X controller, TSECs, RapidIO interconnect, DMA
controller, and CPU, do not all operate at their maximum performance). The frequency specified is the
minimum CPM frequency necessary to run the mentioned protocols concurrently in full duplex.
100BaseT
√√
10BaseT
√√
HDLC
√√√
HDLC_BUS
√
Transparent
√√√
UART
√
Multichannel
√
Table 1. MPC8560 Protocols (continued)
Protocol
Port
TSEC
FCC
SCC
MCC
TC Layer
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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