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參數(shù)資料
| 型號： | KMPC8560VTAQFB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 3/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU POWERQUICC III 783-FCPBGA |
| 標(biāo)準(zhǔn)包裝： | 2 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 1.0GHz |
| 電壓： | 1.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 784-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
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MOTOROLA
MPC8560 PowerQUICC III
11
Integrated Communications Processor Product Brief
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
e500 Core Overview
Extended exception handling
— Supports Book E interrupt model
– Interrupt vector prefix register (IVPR)
– Vector offset registers (IVORs) 0–15 as defined in Book E, plus e500-defined IVORs 32–35
– Exception syndrome register (ESR)
– Book E–defined preempting critical interrupt, including critical interrupt status registers
(CSRR0 and CSRR1) and an rfci instruction
— e500-specific interrupts not defined in Book E architecture
– SPE APU unavailable exception
– Floating-point data exception
– Floating-point round exception
– Performance monitor
Memory management unit (MMU)
— Data L1 MMU
– Four-entry, fully-associative TLB array for variable-sized pages
– 64-entry, four-way set-associative TLB for 4-Kbyte pages
— Instruction L1 MMU
– Four-entry, fully-associative TLB array for variable-sized pages
– 64-entry, four-way set-associative TLB for 4-Kbyte pages
—Unified L2 MMU
– 16-entry, fully-associative TLB array for variable-sized pages
– 256-entry, two-way set-associative TLB for 4-Kbyte pages
— Software reload for TLBs
— Virtual memory support for as much as 4 Gbytes (232) of virtual memory
— Real memory support for as much as 4 Gbytes (232) of physical memory
— Support for big-endian and true little-endian memory on a per-page basis
Power management
— Low power, 1.2-V design
— Dynamic power management on the core minimizes power consumption of functional units,
such as execution units, caches, and MMUs, when they are idle.
— Core power-saving modes: core-halted and core-stopped
— NAP, DOZE, and SLEEP bits in HID0 that can be used to assert nap, doze, and sleep core output
signals to initiate power-saving modes at the integrated-device level
— Internal clock multipliers of 2x, 2.5x, and 3x from bus clock
Testability
— LSSD scan design
— JTAG interface
— ESP support
— ABIST for arrays
—LBIST
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| KMPC8567CVTANGGA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications |
| KMPC8567CVTANGJA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications |
| KMPC8567CVTANJGA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications |
| KMPC8567CVTANJJA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications |
| KMPC8567CVTAQGGA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications |
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