參數(shù)資料
型號： KMPC8241LZQ166D
廠商： Freescale Semiconductor
文件頁數(shù)： 32/58頁
文件大小： 0K
描述： IC MPU 32BIT 166MHZ 357-PBGA
標準包裝： 2
系列： MPC82xx
處理器類型： 32-位 MPC82xx PowerQUICC II
速度： 166MHz
電壓： 1.8V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 托盤
MPC8241 Integrated Processor Hardware Specifications, Rev. 10
38
Freescale Semiconductor
Package Description
DA[10:6]/
PLL_CFG[0:4]
N3 N2 N1 M4 M3
I/O
GVDD_OVDD
—
1, 5, 20
DA[11]
T13
Output
GVDD_OVDD
DRV_PCI
1, 19
DA[12:13]
M16 N16
Output
GVDD_OVDD
DRV_STD_MEM
19
DA[14:15]
B6 D8
Output
GVDD_OVDD
DRV_MEM_CTRL
1, 19
Notes:
1. Multi-pin signals such as AD[31:0] or MDL[0:31] physical package pin numbers are listed in order corresponding to the signal
names. Ex: AD0 is on pin U1, AD1 is on pin U2,..., AD31 is on pin U13.
2. This pin is affected by a programmable PCI_HOLD_DEL parameter.
3. A weak pull-up resistor (2–10 k
Ω) should be placed on this PCI control pin to LVDD.
4. GNT4 is a reset configuration pin with an internal pull-up resistor that is enabled only when in the reset state.
5. This pin is a multiplexed signal and appears more than once in this table.
6. This pin has an internal pull-up resistor that is enabled at all times. The value of the internal pull-up resistor is not guaranteed,
but is sufficient to prevent unused inputs from floating.
7. This pin is a sustained three-state pin as defined by the PCI Local Bus Specification (Rev. 2.2).
8. This pin is an open-drain signal.
9. DL[0] is a reset configuration pin with an internal pull-up resistor that is enabled only when in the reset state. The value of the
internal pull-up resistor is not guaranteed, but is sufficient to ensure that a logic 1 is read into configuration bits during reset.
10.This pin has an internal pull-up resistor that is enabled only when in the reset state. The value of the internal pull-up resistor
is not guaranteed, but is sufficient to ensure that a logic 1 is read into configuration bits during reset.
11.This pin is a reset configuration pin.
12.A weak pull-up resistor (2–10 k
Ω) should be placed on this pin to GVDD_OVDD.
13.VIH and VIL for these signals are the same as the PCI VIH and VIL entries in Table 3.
14.External PCI clocking source or fanout buffer may be required for system if using the MPC8241 DUART functionality because
PCI_CLK[0:3] are not available in DUART mode. Only PCI_CLK4 is available in DUART mode.
15.OSC_IN uses the 3.3-V PCI interface driver, which is 5-V tolerant. See Table 2 for details.
16.This pin can be programmed as driven (default) or as open-drain (in MIOCR 1).
17.All grounded pins are connected together. Connections should not be made to individual pins. The list represents the balls
that are connected to ground.
18.GVDD_OVDD must not exceed VDD/AVDD/AVDD2 by more than 1.8 V at any time including during power-on reset. Note that
GVDD_OVDD pins are all shorted together, PWRRING. The list represents the balls that are connected to PWRRING.
Connections should not be made to individual PWRRING pins.
19.Treat these pins as no connects unless debug address functionality is used.
20.PLL_CFG signals must be driven on reset and must be held for at least 25 clock cycles after the negation of HRST_CTRL
and HRST_CPU in order to be latched.
21.Place a pull-up resistor of 120
Ω or less on the TEST0 pin.
22.SDRAM_CLK[0:3] and SDRAM_SYNC_OUT signals use DRV_MEM_CTRL for chip Rev. 1.1 (A). These signals use
DRV_MEM_CLK for chip Rev. 1.2B.
23.The driver capability of this pin is hardwired to 40
Ω and cannot be changed.
24.Freescale typically expects that customers using the serial port will have sufficient drivers available in the RS232 transceiver
to drive the CTS pin actively as an input if they are using that mode. No pullups would be needed in these circumstances.
25. HRST_CPU/HRST_CTRL must transition from a logic 0 to a logic 1 in less than one SDRAM_SYNC_IN clock cycle for the
device to be in the nonreset state
Table 16. MPC8241 Pinout Listing (continued)
Signal Name
Package Pin Number
Pin Type
Power
Supply
Output
Driver Type
Notes
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