參數(shù)資料
型號: KMC8113TVT3600V
廠商: Freescale Semiconductor
文件頁數(shù): 9/44頁
文件大?。?/td> 0K
描述: IC DSP 300/400MHZ 431FCPGA
標準包裝: 2
系列: StarCore
類型: SC140 內(nèi)核
接口: 以太網(wǎng),I²C,TDM,UART
時鐘速率: 300MHz
非易失內(nèi)存: 外部
芯片上RAM: 1.436MB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.10V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 431-BFBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 431-FCPBGA(20x20)
包裝: 托盤
Electrical Characteristics
MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 1
Freescale Semiconductor
17
In all cases, the power-up sequence must follow the guidelines shown in Figure 8.
The following rules apply:
1.
During time interval A, VDDH should always be equal to or less than the VDD/VCCSYN voltage level.
The duration of interval A should be kept below 10 ms.
2.
The duration of timing interval B should be kept as small as possible and less than 10 ms.
2.5.3
Clock and Timing Signals
The following sections include a description of clock signal characteristics. Table 7 shows the maximum frequency values for
internal (Core, Reference, Bus, and DSI) and external (CLKIN and CLKOUT) clocks. The user must ensure that maximum
frequency values are not exceeded.
Figure 7. Start-Up Sequence: VDD Raised Before VDDH with CLKIN Started with VDDH
Figure 8. Power-Up Sequence for VDDH and VDD/VCCSYN
Table 7. Maximum Frequencies
Characteristic
Maximum in MHz
Core frequency
300/400
Reference frequency (REFCLK)
100/133
Vo
lt
a
g
e
Time
o.5 V
3.3 V
1.1 V
VDDH Nominal
PORESET/TRST asserted
VDD Nominal
CLKIN starts toggling
VDD applied
PORESET/TRST deasserted
1
VDDH applied
VDDH = Nominal
VDD = Nominal
3.3 V
1.2 V
A
B
VDD/VCCSYN
VDDH (IO)
t (time)
V
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