- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄22054 > KMC8113TVT3600V (Freescale Semiconductor)IC DSP 300/400MHZ 431FCPGA PDF資料下載
參數(shù)資料
| 型號： | KMC8113TVT3600V |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 35/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 300/400MHZ 431FCPGA |
| 標(biāo)準(zhǔn)包裝： | 2 |
| 系列： | StarCore |
| 類型： | SC140 內(nèi)核 |
| 接口： | 以太網(wǎng)，I²C，TDM，UART |
| 時鐘速率： | 300MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 1.436MB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.10V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 431-BFBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 431-FCPBGA（20x20） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁當(dāng)前第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 1
Hardware Design Considerations
Freescale Semiconductor
40
If there is an external bus master (BCR[EBM] = 1):
— BR, BG, DBG, and TS must be pulled up.
— EXT_BR[2–3], EXT_BG[2–3], and EXT_DBG[2–3] must be pulled up if multiplexed to the system bus
functionality.
In single-master mode, ABB and DBB can be selected as IRQ inputs and be connected to the non-active value. In other
modes, they must be pulled up.
Note:
The MSC8113 does not support DLL-enabled mode. For the following two clock schemes, ensure that the DLL is
disabled (that is, the DLLDIS bit in the Hard Reset Configuration Word is set).
If no system synchronization is required (for example, the design does not use SDRAM), you can use any of the
available clock modes.
In the CLKIN synchronization mode, use the following connections:
— Connect the oscillator output through a buffer to CLKIN.
— Connect the CLKIN buffer output to the slave device (for example, SDRAM) making sure that the delay path
between the clock buffer to the MSC8113 and the SDRAM is equal (that is, has a skew less than 100 ps).
— Valid clock modes in this scheme are: 0, 7, 15, 19, 21, 23, 28, 29, 30, and 31.
Note:
See the Clock chapter in the MSC8113 Reference Manual for details.
If the 60x-compatible system bus is not used and SIUMCR[PBSE] is set, PPBS can be disconnected. Otherwise, it
should be pulled up.
The following signals: SWTE, DSISYNC, DSI64, MODCK[1–2], CNFGS, CHIPID[0–3], RSTCONF and BM[0–2] are
used to configure the MSC8113 and are sampled on the deassertion of the PORESET signal. Therefore, they should
be tied to GND or VDDH or through a pull-down or a pull-up resistor until the deassertion of the PORESET signal.
When they are used, INT_OUT (if SIUMCR[INTODC] is cleared), NMI_OUT, and IRQxx (if not full drive) signals must
be pulled up.
When the Ethernet controller is enabled and the SMII mode is selected, GPIO10 and GPIO14 must not be connected
externally to any signal line.
Note:
For details on configuration, see the MSC8113 User’s Guide and MSC8113 Reference Manual. For additional
information, refer to the MSC8113 Design Checklist (ANxxxx).
3.4
External SDRAM Selection
The external bus speed implemented in a system determines the speed of the SDRAM used on that bus. However, because of
differences in timing characteristics among various SDRAM manufacturers, you may have use a faster speed rated SDRAM to
assure efficient data transfer across the bus. For example, for 133 MHz operation, you may have to use 133 or 166 MHz
SDRAM. Always perform a detailed timing analysis using the MSC8113 bus timing values and the manufacturer specifications
for the SDRAM to ensure correct operation within your system design. The output delay listed in SDRAM specifications is
usually given for a load of 30 pF. Scale the number to your specific board load using the typical scaling number provided by
the SDRAM manufacturer.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| B82496C3121J | INDUCTOR 120NH .16A 0603 5% |
| TAJC477M004RNJ | CAP TANT 470UF 4V 20% 2312 |
| KMC8112TVT2400V | IC DSP 300MHZ 431FCPBGA |
| GEC10DREH-S734 | CONN EDGECARD 20POS .100 EYELET |
| KMC8112TMP2400V | IC DSP 300MHZ 431FCPBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KMC8113TVT4800V | 功能描述:IC DSP 300/400MHZ 431FCPGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| KMC811E2CFN2 | 制造商:Freescale Semiconductor 功能描述:MCU - Bulk |
| KMC811E2CP2 | 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
| KMC812A4CPV8 | 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
| KMC8144ESVT1000A | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC PACSUN SAMPLE PART RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。