參數(shù)資料
型號： KM68V512A
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 64Kx8 bit Low Power and Low Voltage CMOS Static RAM(64K x8位高速CMOS 靜態(tài) RAM)
中文描述： 64Kx8位低功耗和低電壓的CMOS靜態(tài)RAM（64K的x8位高速的CMOS靜態(tài)RAM）的
文件頁數(shù)： 5/10頁
文件大小： 180K
代理商： KM68V512A
KM68V512A, KM68U512A Family
CMOS SRAM
Revision 3.0
February 1998
5
AC CHARACTERISTICS
(KM68V512B Family:Vcc=3.0~3.6V, KM68U512B Family:Vcc=2.7~3.3V,
Commercial product:T
A
=0 to 70
°
C, Extended product:T
A
=-25 to 85
°
C, Industrial product:T
A
=-40 to 85
°
C)
Parameter List
Symbol
Speed Bins
Units
70ns
85ns
100ns
Min
Max
Min
Max
Min
Max
Read
Read cycle time
t
RC
70
-
85
-
100
-
ns
Address access time
t
AA
-
70
-
85
-
100
ns
Chip select to output
t
CO
-
70
-
85
-
100
ns
Output enable to valid output
t
OE
-
35
-
45
-
50
ns
Chip select to low-Z output
t
LZ
10
-
10
-
10
-
ns
Output enable to low-Z output
t
OLZ
5
-
5
-
5
-
ns
Chip disable to high-Z output
t
HZ
0
25
0
30
0
30
ns
Output disable to high-Z output
t
OHZ
0
25
0
20
0
20
ns
Output hold from address change
t
OH
10
-
10
-
15
-
ns
Write
Write cycle time
t
WC
70
-
85
-
100
-
ns
Chip select to end of write
t
CW
60
-
70
-
80
-
ns
Address set-up time
t
AS
0
-
0
-
0
-
ns
Address valid to end of write
t
AW
60
-
70
-
80
-
ns
Write pulse width
t
WP
55
-
60
-
70
-
ns
Write recovery time
t
WR
0
-
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
25
0
25
0
30
ns
Data to write time overlap
t
DW
30
-
35
-
40
-
ns
Data hold from write time
t
DH
0
-
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
5
-
ns
C
L
1)
1. Including scope and jig capacitance
AC OPERATING CONDITIONS
TEST CONDITIONS
( Test Load and Input/Output Reference)
Input pulse level : 0.4 to 2.2V
Input rising and falling time : 5ns
Input and output reference voltage :1.5V
Output load(see right) : C
L
=100pF+1TTL
1)
C
L
=30pF+1TTL
1. KM68V512AL-7L Family, KM68U512AL-8L Family
DATA RETENTION CHARACTERISTICS
Item
1.
CS
1
≥
Vcc-0.2V, CS
2
≥
Vcc-0.2V( CS
1
controlled) or CS
2
≤
0.2V(CS
2
controlled)
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
V
DR
CS
1
1)
≥
Vcc-0.2V
2.0
-
3.6
V
Data retention current
I
DR
KM68V512AL-L
KM68V512ALE-L
KM68V512ALI-L
Vcc=3.0V, CS
1
≥
Vcc-0.2V,
CS
2
≥
Vcc-0.2V or CS
2
≤
0.2V
-
-
-
-
-
-
10
15
15
μ
A
KM68U512AL-L
KM68U512ALE-L
KM68U512ALI-L
-
-
-
-
-
-
8
10
10
Data retention set-up time
t
SDR
See data retention waveform
0
-
-
ms
Recovery time
t
RDR
5
-
-
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