- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358029 > KM6164002ATE-17 256K X 16 STANDARD SRAM, 17 ns, PDSO44 PDF資料下載
參數(shù)資料
| 型號(hào)： | KM6164002ATE-17 |
| 元件分類： | SRAM |
| 英文描述： | 256K X 16 STANDARD SRAM, 17 ns, PDSO44 |
| 封裝： | 0.400 INCH, TSOP2-44 |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大小： | 197K |
| 代理商： | KM6164002ATE-17 |
KM6164002A, KM6164002AE, KM6164002AI
CMOS SRAM
PRELIMINARY
Rev 2.1
- 5 -
December 1998
WRITE CYCLE*
* The above parameters are also guaranteed at extended and industrial temperature ranges.
Parameter
Symbol
KM6164002A-15
KM6164002A-17
KM6164002A-20
Unit
Min
Max
Min
Max
Min
Max
Write Cycle Time
t
WC
15
-
17
-
20
-
ns
Chip Select to End of Write
t
CW
12
-
13
-
14
-
ns
Address Set-up Time
t
AS
0
-
0
-
0
-
ns
Address Valid to End of Write
t
AW
12
-
13
-
14
-
ns
Write Pulse Width(OE High)
t
WP
12
-
13
-
14
-
ns
Write Pulse Width(OE Low)
t
WP1
15
-
17
-
20
-
ns
UB, LB Valid to End of Write
t
BW
12
-
13
-
14
-
ns
Write Recovery Time
t
WR
0
-
0
-
0
-
ns
Write to Output High-Z
t
WHZ
0
7
0
8
0
9
ns
Data to Write Time Overlap
t
DW
8
-
9
-
10
-
ns
Data Hold from Write Time
t
DH
0
-
0
-
0
-
ns
End Write to Output Low-Z
t
OW
3
-
3
-
3
-
ns
Address
Data Out
Previous Valid Data
Valid Data
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
, UB, LB=V
IL
)
t
AA
t
RC
t
OH
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KM62256DLG-5 | 32Kx8 bit Low Power CMOS Static RAM |
| KM62256DLTGI-7 | 32Kx8 bit Low Power CMOS Static RAM |
| KM62256DLTGI-7L | 32Kx8 bit Low Power CMOS Static RAM |
| KM62256DLRGI-7 | 32Kx8 bit Low Power CMOS Static RAM |
| KM62256DLRGI-7L | 32Kx8 bit Low Power CMOS Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM6164002E | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:CMOS SRAM |
| KM6164002I | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:CMOS SRAM |
| KM6164002J-20 FAB | 制造商:Samsung Semiconductor 功能描述: |
| KM616B4002J-12 | 制造商:SEC 功能描述: |
| KM6-16S-10PN | 制造商:Amphenol Corporation 功能描述:KM AUSTRALIAN PRODUCT - Bulk |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。