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參數(shù)資料
| 型號： | KM6164002ATE-17 |
| 元件分類： | SRAM |
| 英文描述： | 256K X 16 STANDARD SRAM, 17 ns, PDSO44 |
| 封裝： | 0.400 INCH, TSOP2-44 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 197K |
| 代理商： | KM6164002ATE-17 |
KM6164002A, KM6164002AE, KM6164002AI
CMOS SRAM
PRELIMINARY
Rev 2.1
- 4 -
December 1998
TEST CONDITIONS*
* The above parameters are also guaranteed at extended and industrial temperature ranges.
Parameter
Value
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3ns
Input and Output timing Reference Levels
1.5V
Output Loads
See below
AC CHARACTERISTICS
(T
A
=0 to 70
°
C, V
CC
=5.0V
±
10%, unless otherwise noted.)
Output Loads(A)
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
D
OUT
5pF*
480
255
+5.0V
D
OUT
30pF*
480
255
+5.0V
* Including Scope and Jig Capacitance
READ CYCLE*
* The above parameters are also guaranteed at extended and industrial temperature ranges.
Parameter
Symbol
KM6164002A-15
KM6164002A-17
KM6164002A-20
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
t
RC
15
-
17
-
20
-
ns
Address Access Time
t
AA
-
15
-
17
-
20
ns
Chip Select to Output
t
CO
-
15
-
17
-
20
ns
Output Enable to Valid Output
t
OE
-
7
-
8
-
9
ns
UB, LB Access Time
t
BA
-
7
-
8
-
9
ns
Chip Enable to Low-Z Output
t
LZ
3
-
3
-
3
-
ns
Output Enable to Low-Z Output
t
OLZ
0
-
0
-
0
-
ns
UB, LB Enable to Low-Z Output
t
BLZ
0
-
0
-
0
-
ns
Chip Disable to High-Z Output
t
HZ
0
7
0
8
0
9
ns
Output Disable to High-Z Output
t
OHZ
0
7
0
8
0
9
ns
UB, LB Disable to High-Z Output
t
BHZ
0
7
0
8
0
9
ns
Output Hold from Address Change
t
OH
3
-
3
-
3
-
ns
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM6164002E | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:CMOS SRAM |
| KM6164002I | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:CMOS SRAM |
| KM6164002J-20 FAB | 制造商:Samsung Semiconductor 功能描述: |
| KM616B4002J-12 | 制造商:SEC 功能描述: |
| KM6-16S-10PN | 制造商:Amphenol Corporation 功能描述:KM AUSTRALIAN PRODUCT - Bulk |
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