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參數(shù)資料
| 型號： | KM611001L |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1M x 1Bit High-Speed CMOS SRAM |
| 中文描述： | 100萬x 1位高速CMOS SRAM的 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 95K |
| 代理商： | KM611001L |
KM611001/L
CMOS SRAM
Rev 2.0
July-1996
5
Address
Data Out
TIMING DIAGRAMS
TIMING WAVE FORM OF READ CYCLE(1)
(Address Controlled)
(/CS=VIL, /WE=VIH)
tRC
tAA
tOH
Previous Data Valid
Data Valid
TIMING WAVE FORM OF READ CYCLE(2)
(/WE=VIH)
NOTES (READ CYCLE)
/WE is high for read cycle.
All read cycle timing is referenced from the last valid address to the first transition address.
tHZ is defined as the time at which the output achieve the open circuit condition and is not referenced to VOH or
VOL levels.
At any given temperature and voltage condition, tHZ(max.) is less than tLZ(min.) both for a given device and from
device to device.
Transition is measured ± 200mV from steady state voltage with Load(B). This parameter is sampled and not 100%
tested.
Device is continuously selected with /CS=VIL
Address valid prior to coincident with /CS transition low.
Address
/CS
Data Out
Data Valid
High-Z
tCO
tOH
tRC
tAA
t LZ (4,5)
t HZ(3,4,5)
1.
2.
3.
4.
5.
6.
7.
Vcc Supply
Current
tPU
tPD
50%
50%
Icc
Isb
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