參數(shù)資料
型號(hào)： KM44C1005D
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 1M x 4Bit CMOS Quad CAS DRAM with Extended Data Out(1M x 4位CMOS四 CAS 動(dòng)態(tài)RAM(帶擴(kuò)展數(shù)據(jù)輸出))
中文描述： 100萬(wàn)x 4位的CMOS DRAM與四中科院擴(kuò)展數(shù)據(jù)輸出（3米× 4位的CMOS四中科院動(dòng)態(tài)隨機(jī)存儲(chǔ)器（帶擴(kuò)展數(shù)據(jù)輸出））
文件頁(yè)數(shù)： 8/21頁(yè)
文件大?。?/td> 393K
代理商： KM44C1005D
KM44C1005D
CMOS DRAM
An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals.
Transition times are measured between V
IH
(min) and V
IL
(max) and are assumed to be 2ns for all inputs.
Measured with a load equivalent to 2 TTL load and 100pF.
Operation within the
t
RCD
(max) limit insures that
t
RAC
(max) can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then access time is controlled exclusively by
t
CAC
.
Assumes that
t
RCD
≥
t
RCD
(max).
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
oh
or V
ol
.
t
WCS
,
t
RWD
,
t
CWD
,
t
AWD
and
t
CPWD
are non restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If
t
WCS
≥
t
WCS
(min), the cycle is an early write cycle and the data output will remain high impedance for
the duration of the cycle. If
t
CWD
≥
t
CWD
(min),
t
RWD
≥
t
RWD
(min),
t
AWD
≥
t
AWD
(min) and
t
CPWD
≥
t
CPWD
(min) then the cycle is a
read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above con-
ditions is satisfied, the condition of the data out is indeterminate.
Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
These parameters are referenced to the first CAS falling edge in early write cycles and to W falling edge in OE controlled
write cycle and read-modify-write cycles.
Operation within the
t
RAD
(max) limit insures that
t
RAC
(max) can be met.
t
RAD
(max) is specified as a reference point only.
If
t
RAD
is greater than the specified
t
RAD
(max) limit, then access time is controlled by
t
AA
.
These specifiecations are applied in the test mode.
In test mode read cycle, the value of
t
RAC
,
t
AA
,
t
CAC
is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
t
CEZ(MAX),
t
REZ(MAX),
t
OEZ(MAX)
and
t
WEZ(MAX)
define the time at which the output achieves the open circuit condition and are
not referenced to output voltage level.
If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going.
If CAS goes high before RAS high going, the open circuit condition of the output is achieved by RAS high going.
t
ASC
≥
6.0ns, Assumes
t
T=
2.0ns
In order to hold the address latched by the first CASx going low, the parameter
t
CLCH
must be met.
If at least one CAS is low at the falling edge of RAS, DQ will be maintained from the previous cycle.
To initiate a new cycle and clear the data out buffer, all four CAS must be pulsed high for
t
CP.
The last CASx edge to go low.
The last CASx edge to go high.
The first CASx edge to go low.
The first CASx edge to go high.
Output parameter is referenced to corresponding CASx Input.
The last rising CASx edge to next cycle's last rising CASx edge.
The last rising CASx edge to first falling CASx edge.
The first DQx controlled by the first CASx to go low.
The last DQx controlled by the first CASx to go high.
Each CASx must meet minimum pulse width.
The last falling CASx edge to the first rising CASx edge.
7.
6.
5.
10.
9.
8.
13.
12.
11.
15.
14.
3.
2.
1.
4.
16.
19.
18.
17.
21.
22.
20.
24.
23.
26.
27.
25.
NOTES
28.
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