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參數(shù)資料
| 型號(hào)： | KM416S4021B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 2M x 16Bit x 2 Banks Synchronous DRAM(2M x 16位 x2組同步動(dòng)態(tài)RAM) |
| 中文描述： | 200萬(wàn)× 16 × 2銀行同步DRAM（2米× 16位x2組同步動(dòng)態(tài)RAM）的 |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大?。?/td> | 59K |
| 代理商： | KM416S4021B |
KM416S4021B
CMOS SDRAM
REV. 0 Jun. '97
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70
°
C)
Parameter
Symbol
Test Condition
CAS
Latency
Version
Unit
Note
-7
-8
Operating current
(One bank active)
I
CC1
Burst length = 1
t
RC
≥
t
RC
(min)
I
OL
= 0 mA
120
110
mA
1
Precharge standby current in
power-down mode
I
CC2
P
CKE
≤
V
IL
(max), t
CC
= 15ns
2
mA
I
CC2
PS
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
2
Precharge standby current in
non power-down mode
I
CC2
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
20
mA
I
CC2
NS
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
10
Active standby current in
power-down mode
I
CC3
P
CKE
≤
V
IL
(max), t
CC
= 15ns
3
mA
I
CC3
PS
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
2
Active standby current in
non power-down mode
(One bank active)
I
CC3
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
30
mA
I
CC3
NS
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
25
mA
Operating current
(Burst mode)
I
CC4
I
OL
= 0 mA
Page burst
2 Banks activated
t
CCD
= 2CLKs
3
170
150
mA
1
2
120
110
Refresh current
I
CC5
t
RC
≥
t
RC
(min)
160
150
mA
2
Self refresh current
I
CC6
CKE
≤
V
IL
(max)
2
mA
3
1. Measured with outputs open.
2. Refresh period is 64ms.
Notes :
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