參數(shù)資料
型號(hào)： KM416RD16AD
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： CAP ELECT 47UF 100V TG SMD
中文描述： 128/144Mbit RDRAM的256 × 16/18位× 2 * 16屬銀行直接RDRAMTM
文件頁(yè)數(shù)： 44/64頁(yè)
文件大小： 4052K
代理商： KM416RD16AD
Page 41
KM416RD8AC(D)/KM418RD8AC(D)
Direct RDRAM
Rev. 1.01 Oct. 1999
Figure 48: NAP and PDN Exit
Figure 49: NAP Entry/Exit Windows (left) and PDN Entry/Exit Windows (right)
CTM/CFM
DQA8..0
DQB8..0
COL4
..COL0
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
20
T
24
T
28
T
17
T
21
T
25
T
29
T
18
T
22
T
26
T
30
T
19
T
23
T
27
T
31
T
32
T
36
T
40
T
44
T
33
T
37
T
41
T
45
T
34
T
38
T
42
T
46
T
35
T
39
T
43
T
47
ROP
DQS=0
b,c
SCK
CMD
SIO0
SIO1
0
1
0/1
a
0/1
a
PDEV5..0
b
PDEV5..0
b
DQS=1
b
t
S3
t
S3
t
H3
t
H3
t
CE
a
Use 0 for NAP exit, 1 for PDN exit
b
Device selection timing slot is selected by DQS field of NAPX register
The packet is repeated
from SIO0 to SIO1
restricted
Power
State
DQS=0
b
DQS=1
b
d
Exit to STBY or ATTN depends upon whether RLXR was
asserted at NAP or PDN entry time
t
S4
t
H4
restricted
STBY/ATTN
d
NAP/PDN
(
NAPX)t
SCYCLE
)/(
256PDNXt
SCYCLE
)
t
S4
t
H4
COP
XOP
No ROW packets may
overlap the restricted interval
No COL packets may
overlap the restricted interval
if device PDEV is exiting the
NAP-A or PDN-A states
ROP
COP
XOP
c
The DQS field must be written with
“
1
”
for this RDRAM.
If PSX=1 in Init register, then
NAP/PDN exit is broadcast
(no PDEV field).
Effective hold becomes
t
H4
’=t
H4
+[PDNXA 64 t
SCYCLE
+t
PDNXB,MAX
]-[PDNX 256 t
SCYCLE
]
if [PDNX 256 t
SCYCLE
] < [PDNXA 64 t
SCYCLE
+t
PDNXB,MAX
].
CTM/CFM
CMD
SCK
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
20
T
17
T
21
T
18
T
22
T
19
T
23
NAPR
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
20
T
17
T
21
T
18
T
19
t
t
NU0
= 5t
CYCLE
+ (2+NAPX)t
SCYCLE
t
NU1
= 8t
CYCLE
- (0.5t
SCYCLE
)
= 23t
CYCLE
no entry to NNU0
PDNR
nNU1
t
t
PU0
nPU1
t
if NSR=0
if NSR=1
t
PU0
= 5 t
CYCLE
+ (2+256 PDNX) t
SCYCLE
t
PU1
= 8 t
CYCLE
- (0.5 t
SCYCLE
)
= 23 t
CYCLE
if PSR=0
if PSR=1
NAP entry
PDN entry
no entry to NAP or PDN
0
1
NAP exit
0
1
PDN exit
0
1
CTM/CFM
CMD
SCK
ROW2
..ROW0
0
1
相關(guān)PDF資料
PDF描述
KM416RD16C 15VPP 74DB 2 TERM CERAM BUZZER
KM416RD16D 15VPP 86DB 2 TERM CERAM BUZZER
KM416RD2AC 128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
KM416RD2AD 128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
KM416RD2C 128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KM416RD16C 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
KM416RD16D 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
KM416RD2AC 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
KM416RD2AD 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
KM416RD2C 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
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