參數(shù)資料
型號(hào): KM29V64000T
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 8M x 8 Bit NAND Flash Memory(8M x 8位 NAND閃速存儲(chǔ)器)
中文描述: 8米× 8位NAND閃存(8米× 8位的NAND閃速存儲(chǔ)器)
文件頁(yè)數(shù): 22/24頁(yè)
文件大?。?/td> 293K
代理商: KM29V64000T
KM29V64000T
FLASH MEMORY
22
Figure 9. Read ID Operation
READ ID
The device contains a product identification mode, initiated by writing 90H to the command register, followed by an address inpu t of
00H. Two read cycles sequentially output the manufacture code(ECH), and the device code (E6H) respectively. The command regis-
ter remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence.
CE
CLE
I/O
0
~
7
ALE
RE
WE
90H
00
ECH
E6H
Address. 1 cycle
Maker code
Device code
t
CR
t
AR1
t
READID
Figure 10. RESET Operation
RESET
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70H command to the command register, a read cycle output s
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/ B pins are common-wired. RE or CE
dose not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random r ead
cycle, a read command(00H or 50H) should be given before sequential page read cycle.
After Power-up
After Reset
Operation Mode
Read 1
Waiting for next command
FFH
I/O
0
~
7
R/B
Table3. Device Status
t
RST
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