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參數(shù)資料
| 型號： | KM29N32000TS |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 4M x 8 Bit NAND Flash Memory(4M x 8位 NAND閃速存儲器) |
| 中文描述： | 4米× 8位NAND閃存（4米× 8位的NAND閃速存儲器） |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 300K |
| 代理商： | KM29N32000TS |
KM29N32000TS
FLASH MEMORY
8
AC Characteristics for Operatio
NOTE
: 1. If CE goes high within 30ns after the rising edge of the last RE, R/B will not return to V
OL
.
2. The time to Ready depends on the value of the pull-up resistor tied R/ B pin.
3. To break the sequential read cycle, CE must be held high for longer than t
CEH
.
Parameter
Symbol
Min
Max
Unit
Data Transfer from Cell to Register
t
R
-
10
μ
s
ALE to RE Delay(read ID)
t
AR1
150
-
ns
ALE to RE Delay(Read cycle)
t
AR2
50
-
ns
CE to RE Delay( ID read)
t
CR
100
-
ns
Ready to RE Low
t
RR
20
-
ns
RE Pulse Width
t
RP
30
-
ns
WE High to Busy
t
WB
-
100
ns
Read Cycle Time
t
RC
50
-
ns
RE Access Time
t
REA
-
35
ns
RE High to Output Hi-Z
t
RHZ
15
30
ns
CE High to Output Hi-Z
t
CHZ
-
20
ns
RE High Hold Time
t
REH
15
-
ns
Output Hi-Z to RE Low
t
IR
0
-
ns
Last RE High to Busy(at sequential read)
t
RB
-
100
ns
CE High to Ready(in case of interception by CE at read)
(1)
t
CRY
-
50 +tr(R/B)
(2)
ns
CE High Hold Time(at the last serial read)
(3)
t
CEH
100
-
ns
RE Low to Status Output
t
RSTO
-
35
ns
CE Low to Status Output
t
CSTO
-
45
ns
RE High to WE Low
t
RHW
0
-
ns
WE High to RE Low
t
WHR
60
-
ns
Erase Suspend Input to Ready
t
SR
-
500
μ
s
RE access time(Read ID)
t
READID
-
35
ns
Device Resetting Time
(Read/Program/Erase/after erase suspend)
t
RST
-
5/10/500/5
μ
s
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
Min
Max
Unit
CLE Set-up Time
t
CLS
0
-
ns
CLE Hold Time
t
CLH
10
-
ns
CE Setup Time
t
CS
0
-
ns
CE Hold Time
t
CH
10
-
ns
WE Pulse Width
t
WP
25
-
ns
ALE Setup Time
t
ALS
0
-
ns
ALE Hold Time
t
ALH
10
-
ns
Data Setup Time
t
DS
20
-
ns
Data Hold Time
t
DH
10
-
ns
Write Cycle Time
t
WC
50
-
ns
WE High Hold Time
t
WH
15
-
ns
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