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參數(shù)資料
| 型號： | KM29N32000TS |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 4M x 8 Bit NAND Flash Memory(4M x 8位 NAND閃速存儲器) |
| 中文描述： | 4米× 8位NAND閃存（4米× 8位的NAND閃速存儲器） |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 300K |
| 代理商： | KM29N32000TS |
KM29N32000TS
FLASH MEMORY
4
PRODUCT INTRODUCTION
The KM29N32000 is a 33Mbit(34,603,008 bit) memory organized as 8192 rows by 528 columns. Spare sixteen columns are located
from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data transfer
between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that
are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 16 pa ges
formed by one NAND structures, totaling 528 NAND structures of 16 cells. The array organization is shown in Figure 2. The progra m
and read opertions are executed on a page basis, while the erase operation is executed on block basis. The memory array consists
of 512 separately or grouped erasable 8K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
KM29N32000.
The KM29N32000 has addresses multiplexed into 8 I/O
′
s. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written throug h
I/O
′
s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle
except for Block Erase command which requires two cycles : a cycle for erase-setup and another for erase-execution after block
address loading. The 4M byte physical space requires 22 addresses, thereby requiring three cycles for byte-level addressing : co l-
umn address, low row address and high row address, in that order. Page Read and Page Program need the same three address
cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used.
Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of
the KM29N32000.
Table 1. COMMAND SETS
NOTE
: 1. The 00H command defines starting address on the 1st half of registers.
The 01H command defines starting address on the 2nd half of registers.
After data access on the 2nd half of register by the 01H command, the status pointer is
Automatically moved to the 1st half register(00H) on the next cycle.
2. The 50H command is valid only When the SE(pin 40) is low level.
Function
1st. Cycle
2nd. Cycle
Acceptable Command during Busy
Sequential Data Input
80h
-
Read 1
00h/01h
(1)
-
Read 2
50h
(2)
-
Read ID
90h
-
Reset
FFh
-
O
Page Program
10h
-
Block Erase
60h
D0h
Erase Suspend
B0h
-
O
Erase Resume
D0h
-
Read Status
70h
-
O
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相關(guān)代理商/技術(shù)參數(shù) |
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| KM29U128IT | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:16M x 8 Bit NAND Flash Memory |
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| KM29U64000IT | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:8M x 8 Bit NAND Flash Memory |
| KM29U64000T | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:8M x 8 Bit NAND Flash Memory |
| KM29V16000AIT | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:FLASH MEMORY |
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