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參數(shù)資料
| 型號(hào)： | KIT908E624DWBEVB |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 18/39頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | KIT EVAL 908E624 TRPL W/MCU/LIN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | HC08, SMARTMOS™ |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | MM908E624 |
| 所含物品： | 板，線纜，CD |
| 相關(guān)產(chǎn)品： | MM908E624ACEWR2DKR-ND - IC SWITCH TRPL HI MCU/LIN 54SOIC MM908E624ACEWR2CT-ND - IC SWITCH TRPL HI MCU/LIN 54SOIC MM908E624ACDWB-ND - IC TRPL SWITCH MCU/LIN 54-SOIC MM908E624ACDWBR2-ND - IC TRPL SWITCH MCU/LIN 54-SOIC MM908E624AYEWR2-ND - IC TRPL SWITCH MCU/LIN 54-SOIC MM908E624AYEW-ND - IC TRPL SWITCH MCU/LIN 54-SOIC MM908E624ACEWR2TR-ND - IC SWITCH TRPL HI MCU/LIN 54SOIC MM908E624ACEW-ND - IC SWITCH TRIPLE MCU/LIN 54-SOIC |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
25
908E624
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
908E624 SPI INTERFACE AND CONFIGURATION
The serial peripheral interface creates the communication
link between the microcontroller and the analog die of the
908E624.
The interface consists of four pins (see Figure 17):
SS—Slave Select
MOSI—Master-Out Slave-In
MISO—Master-In Slave-Out
SPSCK—Serial Clock
A complete data transfer via the SPI consists of 1 byte.
The master sends 8 bits of control information and the slave
replies with 8 bits of status data.
Figure 17. SPI Protocol
During the inactive phase of the SS (HIGH), the new data
transfer is prepared.
The falling edge of the SS indicates the start of a new data
transfer and puts the MISO in the low-impedance state and
latches the analog status data (Register read data).
With the rising edge of the SPI clock, SPSCK the data is
moved to MISO/MOSI pins. With the falling edge of the SPI
clock SPSCK the data is sampled by the Receiver.
The data transfer is only valid if exactly 8 sample clock
edges are present in the active (low) phase of SS.
The rising edge of the slave select SS indicates the end of
the transfer and latches the write data (MOSI) into the
register The SS high forces MISO to the high-impedance
state.
SPI REGISTER OVERVIEW
Table 7 summarizes the SPI Register bit meaning, reset
value, and bit reset condition.
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Register write data
Register read data
Rising edge of SPSCK
Change MISO/MOSI Output
Falling edge of SPSCK
Sample MISO/MOSI Input
Write data latch
SS
MOSI
MISO
SPSCK
Read data latch
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