OPERATIONAL MODES INTERRUPTS In Normal (Ru" />
參數(shù)資料
型號(hào)： KIT908E624DWBEVB
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 13/39頁(yè)
文件大小： 0K
描述： KIT EVAL 908E624 TRPL W/MCU/LIN
標(biāo)準(zhǔn)包裝： 1
系列： HC08, SMARTMOS™
類(lèi)型： MCU
適用于相關(guān)產(chǎn)品： MM908E624
所含物品： 板，線(xiàn)纜，CD
相關(guān)產(chǎn)品： MM908E624ACEWR2DKR-ND - IC SWITCH TRPL HI MCU/LIN 54SOIC
MM908E624ACEWR2CT-ND - IC SWITCH TRPL HI MCU/LIN 54SOIC
MM908E624ACDWB-ND - IC TRPL SWITCH MCU/LIN 54-SOIC
MM908E624ACDWBR2-ND - IC TRPL SWITCH MCU/LIN 54-SOIC
MM908E624AYEWR2-ND - IC TRPL SWITCH MCU/LIN 54-SOIC
MM908E624AYEW-ND - IC TRPL SWITCH MCU/LIN 54-SOIC
MM908E624ACEWR2TR-ND - IC SWITCH TRPL HI MCU/LIN 54SOIC
MM908E624ACEW-ND - IC SWITCH TRIPLE MCU/LIN 54-SOIC
Analog Integrated Circuit Device Data
20
Freescale Semiconductor
908E624
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
INTERRUPTS
In Normal (Run) mode the 908E624 has four different
interrupt sources. An interrupt pulse on the IRQ_A pin is
generated to report a fault to the MCU. All interrupts are not
maskable and cannot be disabled.
After an Interrupt the INTSRC bit in the SPI Status register
is set, indicating the source of the event. This interrupt source
information is only transferred once, and the INTSRC bit is
cleared automatically.
Low-Voltage Interrupt
Low-voltage interrupt (LVI) is related to external supply
voltage VSUP1. If this voltage falls below the LVI threshold,
it will set the LVF bit in the SPI Status register and an interrupt
will be initiated. The LVF bit remains set as long as the Low-
voltage condition is present.
During Sleep and Stop mode the low-voltage interrupt
circuitry is disabled.
High-voltage Interrupt
High-voltage interrupt (HVI) is related to external supply
voltage VSUP1. If this voltage rises above the HVI threshold,
it will set the HVF bit in the SPI Status register and an
interrupt will be initiated. The HVF bit remains set as long as
the high-voltage condition is present.
During Sleep and Stop mode the high-voltage interrupt
circuitry is disabled.
Wake-up Interrupts
In Stop mode the IRQ_A pin reports wake-up events on the
L1, L2, or the LIN bus to the MCU. All wake-up interrupts are
not maskable and cannot be disabled.
After a wake-up interrupt, the INTSRC bit in the Serial
Peripheral Interface (SPI) Status register is set, indicating the
source of the event. This wake-up source information is only
transferred once, and the INTSRC bit is cleared
automatically.
Figure 12, page 21, describes the Stop/Wake-up
procedure.
Voltage Regulator Temperature Prewarning (VDDT)
Voltage regulator temperature prewarning (VDDT) is
generated if the voltage regulator temperature is above the
TPRE threshold. It will set the VDDT bit in the SPI Status
register and an interrupt will be initiated. The VDDT bit
remains set as long as the error condition is present.
During Sleep and Stop mode the voltage regulator
temperature prewarning circuitry is disabled.
High Side Switch Thermal Shutdown (HSST)
The high side switch thermal shutdown HSST is generated
if one of the high side switches HS1:HS3 is above the HSST
threshold, it will shutdown all high side switches, set the
HSST flag in the SPI Status register and an interrupt will be
initiated. The HSST bit remains set as long as the error
condition is present.
During Sleep and Stop mode the high side switch thermal
shutdown circuitry is disabled.
Table 6. Operating Modes Overview
Device
Mode
Voltage Regulator
Wake-up
Capabilities
RST_A
Output
Watchdog
Function
HS1, HS2,
and HS3
LIN Interface
Sense
Amplifier
Reset
VDD ON
N/A
LOW
Disabled
Recessive only
Not active
Normal
Request
VDD ON
N/A
HIGH
150 ms time out if
WD enabled
Enabled
Transmit and
receive
Not active
Normal
(Run)
VDD ON
N/A
HIGH
Window WD if
enabled
Enabled
Transmit and
receive
Active
Stop
VDD ON with limited
current capability
LIN wake-up,
L1, L2 state change,
SS
rising edge
HIGH
Disabled
Recessive state with
wake-up capability
Not active
Sleep
VDD OFF
LIN wake-up
L1, L2 state change
LOW
Disabled
Recessive state with
wake-up capability
Not active
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