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參數(shù)資料
| 型號(hào)： | KIT33298DWEVB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 15/28頁 |
| 文件大小： | 0K |
| 描述： | KIT EVAL FOR MC33298 SMART SW |
| 標(biāo)準(zhǔn)包裝： | 1 |
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Analog Integrated Circuit Device Data
22
Freescale Semiconductor
33298
FUNCTIONAL DESCRIPTION
FAULT LOGIC OPERATION
ARCHIVE
INFORMATION
ARCHIVE
INFORMATION
upon the next command word being entered, a logic low
came back on SO, for that specific output’s corresponding bit,
an Output-OFF Open-Load fault would be indicated. The
resulting SO bit, for that specific output, would be different
from that entered during the previous word for that SI bit,
indicating the fault. The eight output-off open-load faults are
therefore most easily detected.
If for a specific output, the initial SI command bit were a
logic low, calling for the output to be programmed on; upon
the next word command being entered, the corresponding bit
came back with a logic high on SO, an output over-current
fault would be indicated. An over-current fault is always
reported by the SO output and is independent of the logic
state existing on the SFPD pin. When the SFPD pin is in a
logic high state, an over-current condition will be reported on
the SO pin. However, limiting output current is in effect and
the output is permitted to operate if the over-current condition
does not drive output into an over-temperature fault. An over-
temperature fault will shutdown the specific output effected
for the duration of the over-temperature condition.
Over-current and over-temperature faults are often
related. Turning the effected output switches OFF and
waiting for some time to allow the output to cool down should
make these types of faults go away. Soft over-current faults
can sometimes be determined over hard short faults and over
temperature faults by observing the time required for the
device to recover. However, in general over-current and over-
temperature faults can not be differentiated in normal
application usage.
An advantage of the synchronous serial output is multiple
faults can be detected with only one (SO) pin being used for
fault status reporting.
If VPWR experiences an over-voltage condition, all outputs
will immediately be turned OFF and remain latched off. A new
command word is required to turn the outputs back on
following an over-voltage condition.
OUTPUT VOLTAGE CLAMPING
Each output of the 33298 incorporates an internal voltage
clamp to provide fast turn-off and transient protection of the
output. Each clamp independently limits the drain to source
voltage to 65V at drain currents of 0.5A and keeps the output
transistors from avalanching by causing the transient energy
to be dissipated in the linear mode. See Figure 21. The total
energy clamped (EJ) can be calculated by multiplying the
current area under the current curve (IA) times the clamp
voltage (VCL) times the duration the clamp is active (t).
Characterization of the output clamps, using a single pulse
non-repetitive method at 0.5A, indicate the maximum energy
to be 50mJ at 150
°C junction temperature per output.
Figure 21. Output Voltage Clamping
THERMAL CHARACTERIZATION
THERMAL MODEL
Logic functions take up a very small area of the die and
generate negligible power. In contrast, the output transistors
take up most of the die area and are the primary contributors
of power generation. The thermal model illustrated in
Figure 22 was developed for the 33298 mounted on a typical
PC board. The model is accurate for both steady state and
transient thermal conditions. The components RD0 through
RD7 represent the steady state thermal resistance of the
silicon die for transistor outputs 0 through 7, while CD0
through CD7 represent the corresponding thermal
capacitance of the silicone die translator outputs and plastic.
The device area and die thickness determine the values of
these specific components.
The thermal impedance of the package from the internal
mounting flag to the outside environment is represented by
the terms RPKG and CPKG. The steady state thermal
resistance of leads and the PC board make up the steady
state package thermal resistance, RPKG. The thermal
capacitance of the package is made up of the combined
capacitance of the flag and the PC board. The mode
compound was not modeled as a specific component but it is
factored into the other overall component values.
The battery voltage in the thermal model represents the
ambient temperature the device and PC board are subjected
to.The IPWR current source represents the total power
dissipation and is calculated by totalling the power dissipation
of each individual output transistor. This is easily
accomplished by knowing RDS(ON) and load current of the
individual outputs.
Very satisfactory steady state and transient results are
experienced with this thermal model. Tests indicate the
model accuracy to have less than 10 percent error. Output
interaction with an adjacent output is believed to be the main
contributor to the thermal inaccuracy. Tests indicate little or
no detectable thermal affects caused by distant output
transistors isolated by one or more other outputs. Tests were
conducted with the device mounted on a typical PC board
placed horizontally in a 33 cubic inch still air enclosure. The
PC board was made of FR4 material measuring 2.5 by 2.5
Current
Area (IA)
VPWR
Time
GND
Drain-to-Source ON
Voltage(VDS(ON))
Drain Current
(ID = 0.5A)
Drain-to-Source Clamp
Voltage (VCL = 65V)
Drain Voltage
Clamp Energy
(EJ = IA x VCL x t)
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