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參數(shù)資料
| 型號： | KD16901 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Audio Effect Processor(音頻效果處理器) |
| 中文描述： | 音頻效果器（音頻效果處理器） |
| 文件頁數(shù)： | 18/68頁 |
| 文件大?。?/td> | 381K |
| 代理商： | KD16901 |
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HARDWARE DESCRIPTION
AUDIO EFFECT PROCESSOR
2-18
I
2
C Bus Interface
The KD16901 can be controlled by a microcontroller via the 2-line I
2
C bus, SDA (Serial Data Line) and SCL (Serial
Clock Line). Both lines must be connected to a positive supply via pull-up resistor. Data transfer may be initiated
only when the bus is not busy. When the bus is free, both lines are high. The data on the SDA line must be stable
during the high period of clock, SCL. When the SCL is low, the SDA can change. Every byte transferred through
the SDA line must contain 8 bits including programmable slave address and read/write direction control bit. Each
byte must be followed by acknowledge bit which is sent back to the microcontroller by the KD16901 by pulling down
the SDA line. The MSB is transferred first. The setup and hold time on the SCL and SDA lines can be found in I
2
C
Specification by Philips.
I
2
C bus interface start and stop condition
The start condition is high to low transition of the SDA line while the SCL is high. The stop condition is low to high
transition of the SDA line while SCL is high.
Figure 8. Data Validity and Start/Stop Condition in I
2
C Bus
I
2
C Bus Interface Acknowledge
The acknowledge related clock pulse is generated by a microcontroller. The transmitter releases the SDA line
(high) during the acknowledge clock pulse. The receiver must pull down the SDA line during the acknowledge clock
pulse so that it remains stable low during the high period of this clock pulse. The slave-transmitter generates
negative acknowledge when read operation processes. The negative acknowledge is generated by a master
(microcontroller).
SCL
SDA
Data Valid
Change
of Data
Allowed
SCL
SDA
S
Stop
Condition
Start
Condition
P
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