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參數(shù)資料
| 型號(hào)： | KBE00S009M-D411 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1Gb NAND x 2 + 256Mb Mobile SDRAM x 2 |
| 中文描述： | 1Gb的NAND × 2 256Mb的移動(dòng)SDRAM × 2 |
| 文件頁數(shù)： | 34/86頁 |
| 文件大?。?/td> | 1898K |
| 代理商： | KBE00S009M-D411 |
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MCP MEMORY
34
KBE00S009M-D411
Revision 1.0
May 2005
Restriction in addressing with Multi Plane Page Program
While any block in each plane may be addressable for Multi-Plane Page Program, the five least significant addresses(A9-A13) for
the selected pages at one operation must be the same. Figure 12 shows an example where 2nd page of each addressed block is
selected for four planes. However, any arbitrary sequence is allowed in addressing multiple planes as shown in Figure13.
80h
Plane 2
11h
80h
11h
80h
11h
80h
10h
Plane 0
Plane3
Plane 1
Plane 0
(2,048 Blocks)
Plane 1
(2,048 Blocks)
Plane 2
(2,048 Blocks)
Plane 3
(2,048 Blocks)
Page 0
Page 1
Page 31
Page 30
Block 0
Page 0
Page 1
Page 31
Page 30
Block 1
Page 0
Page 1
Page 31
Page 30
Block 2
Page 0
Page 1
Page 31
Page 30
Block 3
Figure 14. Multi-Plane Page Program & Read Status Operation
80h
A
0
~ A
7
& A
9
~ A
27
528 bytes
I/O
0
~
7
R/B
Address & Data Input
I/O
Pass
10h
71h
Fail
t
PROG
Last Plane input
Multi-Plane Block Erase into Plane 0~3 or Plane 4~7
Basic concept of Multi-Plane Block Erase operation is identical to that of Multi-Plane Page Program. Up to four blocks, one from each
plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command followed by three
address cycles) may be repeated up to four times for erasing up to four blocks. Only one block should be selected from each plane.
The Erase Confirm command initiates the actual erasing process. The completion is detected by analyzing R/B pin or Ready/Busy
status (I/O 6). Upon the erase completion, pass/fail status of each block is examined by reading extended pass/fail status(I/O 1
through I/O 4).
Figure 17. Four Block Erase Operation
60h
A
0
~ A
7
& A
9
~ A
27
I/O
X
R/B
Address
(3 Cycle)
60h
60h
60h
D0h
71h
I/O
Pass
Fail
t
BERS
Address
(3 Cycle)
Address
(3 Cycle)
Address
(3 Cycle)
Figure 12. Multi-Plane Program & Read Status Operation
Figure 13. Addressing Multiple Planes
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