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參數(shù)資料
| 型號： | K7I321882M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 元件分類： | DRAM |
| 英文描述： | 1Mx36 & 2Mx18 DDRII CIO b2 SRAM |
| 中文描述： | 1Mx36 |
| 文件頁數(shù)： | 11/17頁 |
| 文件大?。?/td> | 377K |
| 代理商： | K7I321882M |
1Mx36 & 2Mx18 DDRII CIO b2 SRAM
- 11 -
Rev 2.1
July. 2004
K7I323682M
K7I321882M
AC TIMING CHARACTERISTICS
(V
DD
=1.8V
±
0.1V, T
A
=0
°
C to +70
°
C)
Notes
: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control signal are R and W.
In case of BW
0
,BW
1
(BW
2
, BW
3
, also for x36) signal follow the data setup/hold times.
3. If C,C are tied high, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX
1
is bigger than tCHQZ.
The specs as shown do not imply bus contention beacuse tCHQX
1
is a MIN parameter that is worst case at totally different test conditions
(0
°
C, 1.9V) than tCHQZ, which is a MAX parameter(worst case at 70
°
C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
PARAMETER
SYMBOL
-25
-20
-16
UNITS NOTES
MIN
MAX
MIN
MAX
MIN
MAX
Clock
Clock Cycle Time (K, K, C, C)
t
KHKH
4.00
6.30
5.00
7.88
6.00
8.40
ns
Clock Phase Jitter (K, K, C, C)
t
KC var
0.20
0.20
0.20
ns
5
Clock High Time (K, K, C, C)
t
KHKL
1.60
2.00
2.40
ns
Clock Low Time (K, K, C, C)
t
KLKH
1.60
2.00
2.40
ns
Clock to Clock (K
↑
→
K
↑
, C
↑
→
C
↑
)
Clock to data clock (K
↑
→
C
↑
, K
↑→
C
↑
)
t
KHKH
1.80
2.20
2.70
ns
t
KHCH
0.00
1.80
0.00
2.30
0.00
2.80
ns
DLL Lock Time (K, C)
t
KC lock
1024
1024
1024
cycle
6
K Static to DLL reset
t
KC reset
30
30
30
ns
Output Times
C, C High to Output Valid
t
CHQV
0.45
0.45
0.50
ns
3
C, C High to Output Hold
t
CHQX
-0.45
-0.45
-0.50
ns
3
C, C High to Echo Clock Valid
t
CHCQV
0.45
0.45
0.50
ns
C, C High to Echo Clock Hold
t
CHCQX
-0.45
-0.45
-0.50
ns
CQ, CQ High to Output Valid
t
CQHQV
0.30
0.35
0.40
ns
CQ, CQ High to Output Hold
t
CQHQX
-0.30
-0.35
-0.40
ns
C, High to Output High-Z
t
CHQZ
0.45
0.45
0.50
ns
3
C, High to Output Low-Z
t
CHQX1
-0.45
-0.45
-0.50
ns
3
Setup Times
Address valid to K rising edge
t
AVKH
0.50
0.60
0.70
ns
Control inputs valid to K rising edge
t
IVKH
0.50
0.60
0.70
ns
2
Data-in valid to K, K rising edge
t
DVKH
0.35
0.40
0.50
ns
Hold Times
K rising edge to address hold
t
KHAX
0.50
0.60
0.70
ns
K rising edge to control inputs hold
t
KHIX
0.50
0.60
0.70
ns
K, K rising edge to data-in hold
t
KHDX
0.35
0.40
0.50
ns
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