- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374293 > K7D803671B-HC30 (SAMSUNG SEMICONDUCTOR CO. LTD.) 256Kx36 & 512Kx18 SRAM PDF資料下載
參數(shù)資料
| 型號： | K7D803671B-HC30 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Kx36 & 512Kx18 SRAM |
| 中文描述： | 256Kx36 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 270K |
| 代理商： | K7D803671B-HC30 |
Rev 4.0
256Kx36 & 512Kx18 SRAM
- 11
January. 2002
K7D801871B
K7D803671B
NOP
CONTINUE
K
K
B1
G
SA
t
AVKH
t
KHAX
CQ
NOP
1
2
3
4
5
6
7
8
10
12
11
B2
B3
CQ
DQ
READ
(burst of 4)
(burst of 4)
9
READ
READ
(burst of 2)
NOP
WRITE
CONTINUE
WRITE
(burst of 4)
READ
CONTINUE
READ
READ
(burst of 4)
CONTINUE
READ
Q
X2
Q
01
Q
02
Q
03
Q
04
Q
51
Q
52
Q
53
Q
54
Q
11
Q
12
D
21
D
23
D
24
D
22
Q
31
t
BVKH
t
KHBX
t
CHQZ
t
KXCH
t
CHLZ
t
CHQV
t
CHQX
t
GHQZ
t
DVKH
t
KHDX
t
GLQX
t
GLQV
t
KHKH
t
GHQX
UNDEFINED
DON’T CARE
NOTE
1. Q
01
refers to output from address A. Q
02
refers to output from the next internal burst address following A, etc.
2. Outputs are disabled(High-Z) one clock cycle after NOP detected or after no pending data requests are present.
3. Doing more than one Read Continue or Write Continue will cause the address to wrap around.
A
0
A
1
A
2
A
3
A
5
TIMING WAVEFORMS FOR DOUBLE DATA RATE CYCLES
(Burst Length=4, 2)
相關PDF資料 |
PDF描述 |
|---|---|
| K7D803671B-HC33 | 256Kx36 & 512Kx18 SRAM |
| K7D803671B-HC35 | 256Kx36 & 512Kx18 SRAM |
| K7D803671B-HC37 | 256Kx36 & 512Kx18 SRAM |
| K7I321882M | 1Mx36 & 2Mx18 DDRII CIO b2 SRAM |
| K7I323682M | 1Mx36 & 2Mx18 DDRII CIO b2 SRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| K7D803671B-HC33 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 SRAM |
| K7D803671B-HC33000 | 制造商:Samsung 功能描述:8MSYNCDOUBLE DATA RATE SRAMX36BGA - Bulk |
| K7D803671B-HC33T00 | 制造商:Samsung Semiconductor 功能描述:8MSYNCDOUBLE DATA RATE SRAMX36BGA, T/R - Tape and Reel |
| K7D803671B-HC35 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 SRAM |
| K7D803671B-HC37 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 SRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。