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參數(shù)資料
| 型號： | K6R4008V1D-JC |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1Mx4 Bit High Speed Static RAM(3.3V Operating). Operated at Commercial and Industrial Temperature Ranges |
| 中文描述： | 1Mx4位高速靜態(tài)RAM（3.3V的）。在商用和工業(yè)溫度范圍運營 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 239K |
| 代理商： | K6R4008V1D-JC |
K6R4008V1D
CMOS SRAM
PRELIMINARY
Rev. 2.0
July 2004
- 7 -
Address
Data Out
Previous Valid Data
Valid Data
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
)
t
AA
t
RC
t
OH
NOTES(
WRITE CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V
OH
or
V
OL
levels.
4. At any given temperature and voltage condition, t
HZ
(Max.) is less than t
LZ
(Min.) both for a given device and from device to
device.
5. Transition is measured
±
200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=V
IL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
WRITE CYCLE*
* The above parameters are also guaranteed at industrial temperature range.
Parameter
Symbol
K6R4008V1D-08
K6R4008V1D-10
Unit
Min
Max
Min
Max
Write Cycle Time
t
WC
8
-
10
-
ns
Chip Select to End of Write
t
CW
6
-
7
-
ns
Address Set-up Time
t
AS
0
-
0
-
ns
Address Valid to End of Write
t
AW
6
-
7
-
ns
Write Pulse Width(OE High)
t
WP
6
-
7
-
ns
Write Pulse Width(OE Low)
t
WP1
8
-
10
-
ns
Write Recovery Time
t
WR
0
-
0
-
ns
Write to Output High-Z
t
WHZ
0
4
0
5
ns
Data to Write Time Overlap
t
DW
4
-
5
-
ns
Data Hold from Write Time
t
DH
0
-
0
-
ns
End of Write to Output Low-Z
t
OW
3
-
3
-
ns
Valid Data
High-Z
t
RC
CS
Address
OE
Data out
t
HZ(3,4,5)
t
AA
t
CO
t
OE
t
OLZ
t
LZ(4,5)
t
OHZ
t
PU
t
PD
50%
50%
V
CC
Current
I
CC
I
SB
t
DH
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
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