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    參數(shù)資料
    型號(hào): K6R1004V1D
    廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
    英文描述: 64Kx16 Bit High-Speed CMOS Static RAM(3.3V Operating) Operated at Commercial and Industrial Temperature Ranges.
    中文描述: 64Kx16位高速CMOS靜態(tài)RAM(3.3V的)在商業(yè)和工業(yè)溫度范圍操作。
    文件頁數(shù): 3/9頁
    文件大?。?/td> 192K
    代理商: K6R1004V1D
    PRELIMINARY
    PRELIMINARY
    CMOS SRAM
    Rev. 3.0
    July 2004
    - 3 -
    K6R1004V1D
    256K x 4 Bit (with OE) High-Speed CMOS Static RAM(3.3V Operating)
    FEATURES
    Fast Access Time 8,10ns(Max.)
    Low Power Dissipation
    Standby (TTL) : 20mA(Max.)
    (CMOS) : 5mA(Max.)
    Operating K6R1004V1D-08: 80mA(Max.)
    K6R1004V1D-10: 65mA(Max.)
    Single 3.3
    ±
    0.3V Power Supply
    TTL Compatible Inputs and Outputs
    Fully Static Operation
    - No Clock or Refresh required
    Three State Outputs
    Center Power/Ground Pin Configuration
    Standard Pin Configuration :
    K6R1004V1D-J : 32-SOJ-400
    K6R1004V1D-K : 32-SOJ-400 (Lead-Free)
    Operating in Commercial and Industrial Temperature range.
    GENERAL DESCRIPTION
    The K6R1004V1D is a 1,048,576-bit high-speed Static Random
    Access Memory organized as 262,144 words by 4 bits.
    The K6R1004V1D uses 4 common input and output lines and
    has an output enable pin which operates faster than address
    access time at read cycle. The device is fabricated using
    SAMSUNG
    s advanced CMOS process and designed for
    high-speed circuit technology. It is particularly well suited for
    use in high-density high-speed system applications. The
    K6R1004V1D is packaged in a 400 mil 32-pin plastic SOJ.
    PIN FUNCTION
    Pin Name
    Pin Function
    A
    0
    - A
    17
    Address Inputs
    WE
    Write Enable
    CS
    Chip Select
    OE
    Output Enable
    I/O
    1
    ~ I/O
    4
    Data Inputs/Outputs
    V
    CC
    Power(+3.3V)
    V
    SS
    Ground
    N.C
    No Connection
    PIN CONFIGURATION
    (Top View)
    Clk Gen.
    I/O
    1
    ~ I/O
    4
    CS
    WE
    OE
    FUNCTIONAL BLOCK DIAGRAM
    R
    Data
    Cont.
    Column Select
    CLK
    Gen.
    Pre-Charge Circuit
    Memory Array
    512 Rows
    512x4 Columns
    I/O Circuit &
    SOJ
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    15
    16
    32
    31
    30
    29
    28
    27
    26
    25
    24
    23
    22
    21
    20
    19
    18
    17
    A
    17
    A
    16
    A
    15
    A
    14
    A
    13
    OE
    I/O
    4
    Vss
    Vcc
    I/O
    3
    A
    12
    A
    11
    A
    10
    A
    9
    A
    8
    N.C
    N.C
    A
    0
    A
    1
    A
    2
    A
    3
    CS
    I/O
    1
    Vcc
    Vss
    I/O
    2
    WE
    A
    4
    A
    5
    A
    6
    A
    7
    N.C
    A
    10
    A
    11
    A
    12
    A
    13
    A
    14
    A
    15
    A
    0
    A
    1
    A
    2
    A
    3
    A
    4
    A
    5
    A
    6
    A
    7
    A
    8
    A
    9
    A
    16
    A
    17
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