參數(shù)資料
型號(hào)： K4T56163QI-ZLD50
元件分類(lèi)： DRAM
英文描述： 16M X 16 SYNCHRONOUS DRAM, 0.5 ns, PBGA84
封裝： ROHS COMPLIANT, FBGA-84
文件頁(yè)數(shù)： 14/42頁(yè)
文件大?。?/td> 727K
代理商： K4T56163QI-ZLD50
Rev. 1.0 October 2007
DDR2 SDRAM
K4T56163QI
21 of 42
15.0 Specific Notes for dedicated AC parameters
1. User can choose which active power down exit timing to use via MRS (bit 12). tXARD is expected to be used for fast active power down exit timing.
tXARDS is expected to be used for slow active power down exit timing.
2. AL = Additive Latency.
3. This is a minimum requirement. Minimum read to precharge timing is AL + BL / 2 provided that the tRTP and tRAS(min) have been satisfied.
4. A minimum of two clocks (2 x tCK or 2 x nCK) is required irrespective of operating frequency.
5. Timings are specified with command/address input slew rate of 1.0 V/ns.
6. Timings are specified with DQs, DM, and DQS’s (DQS/RDQS in single ended mode) input slew rate of 1.0V/ns.
7. Timings are specified with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/ns in
differential strobe mode and a slew rate of 1.0 V/ns in single ended mode.
8. Data setup and hold time derating.
Table 1 - DDR2-400/533 tDS/tDH derating with differential data strobe
Table 2 - DDR2-667/800 tDS/tDH derating with differential data strobe
tDS, tDH Derating Values of DDR2-400, DDR2-533 (ALL units in ‘ps’, the note applies to entire Table)
DQS,DQS Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4V/ns
1.2V/ns
1.0V/ns
0.8V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
DQ
Siew
rate
V/ns
2.0
125
45
125
45
125
45
-
----
---
----
1.5
83
21
83
21
83
21
95
33
---
----
1.0
0
12
24
-
---
----
0.9
-
-11
-14
-11
-14
1
-2
13
10
25
22
--
----
0.8
---
-
-25
-31
-13
-19
-1
-7
11
5
23
17
----
0.7
---
-31
-42
-19
-30
-7
-18
5
-6
17
6
-
0.6
---
----
-
-43
-59
-31
-47
-19
-35
-7
-23
5
-11
0.5
---
----
---
-74
-89
-62
-77
-50
-65
-38
-53
0.4
---
----
-
-127
-140
-115
-128
-103
-116
tDS, tDH Derating Values for DDR2-667, DDR2-800 (ALL units in ‘ps’, the note applies to entire Table)
DQS,DQS Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4V/ns
1.2V/ns
1.0V/ns
0.8V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
DQ
Slew
rate
V/ns
2.0
100
45
45
100
45
-
-----------
1.5
67
21
67
21
67
21
79
33
----------
1.0
00000
0
12
24
--------
0.9
-
-5
-14
-5
-14
7
-2
19
10
31
22
------
0.8
----
-13
-31
-1
-19
11
-7
23
5
35
17
----
0.7
------
-10
-42
2
-30
14
-18
26
-6
38
6
--
0.6
-------
-
-10
-59
2
-47
14
-35
26
-23
38
-11
0.5
-------
---
-24
-89
-12
-77
0
-65
12
-53
0.4
-------
-----
-52
-140
-40
-128
-28
-116
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K4T56163QN 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:Consumer Memory
K4T56163QN-HCE6000 制造商:Samsung SDI 功能描述:DRAM Chip DDR2 SDRAM 256M-Bit 16Mx16 1.8V 84-Pin FBGA Tray
K4T56163QN-HCE6T00 制造商:Samsung SDI 功能描述:
K4T56163QN-ZCE6T00 制造商:Samsung 功能描述:256 SDRAM X16 - Tape and Reel
K4T56163QN-ZCE7000 制造商:Samsung 功能描述:DDR2 SDRAM 32MX16 47H32M16 PBF FBGA 1.8V PLASTIC 512M - Trays
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