參數(shù)資料
型號： K4R881869
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM
中文描述： 288Mbit RDRAM的為512k × 18位× 2 * 16屬銀行直接RDRAMTM
文件頁數(shù)： 49/64頁
文件大?。?/td> 4084K
代理商： K4R881869
Page 47
Direct RDRAM
K4R881869M
Rev. 0.9 Jan. 2000
Preliminary
RSL - Clocking
Figure 53 is a timing diagram which shows the detailed
requirements for the RSL clock signals on the Channel.
The CTM and CTMN are differential clock inputs used for
transmitting information on the DQA and DQB, outputs.
Most timing is measured relative to the points where they
cross. The t
CYCLE
parameter is measured from the falling
CTM edge to the falling CTM edge. The t
CL
and t
CH
param-
eters are measured from falling to rising and rising to falling
edges of CTM. The t
CR
and t
CF
rise- and fall-time parame-
ters are measured at the 20% and 80% points.
The CFM and CFMN are differential clock outputs used for
receiving information on the DQA, DQB, ROW and COL
outputs. Most timing is measured relative to the points
where they cross. The t
CYCLE
parameter is measured from
the falling CFM edge to the falling CFM edge. The t
CL
and
t
CH
parameters are measured from falling to rising and rising
to falling edges of CFM. The t
CR
and t
CF
rise- and fall-time
parameters are measured at the 20% and 80% points.
The t
TR
parameter specifies the phase difference that may be
tolerated with respect to the CTM and CFM differential
clock inputs (the CTM pair is always earlier).
Figure 53: RSL Timing - Clock Signals
V
CIH
50%
V
CIL
80%
20%
CTM
CTMN
V
CIH
50%
V
CIL
80%
20%
CFM
CFMN
t
TR
t
CF
t
CF
t
CR
t
CR
t
CYCLE
t
CL
t
CH
t
CF
t
CF
t
CR
t
CR
t
CYCLE
t
CL
t
CH
V
CM
V
X+
V
X-
V
CM
V
X+
V
X-
相關(guān)PDF資料
PDF描述
K4R881869M 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM
K4R881869M-NbCcG6 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM
K4R881869M-NCK7 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM
K4R881869M-NCK8 288Mbit RDRAM 512K x 18 bit x 2*16 Dependent Banks Direct RDRAMTM
K4S280432A 128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K4R881869D 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256/288Mbit RDRAM(D-die)
K4R881869D-FCM8 制造商:Samsung Electro-Mechanics 功能描述:16M X 18 DIRECT RAMBUS DRAM, PBGA92
K4R881869EFCT9 制造商:Samsung Semiconductor 功能描述:
K4R881869E-GCM8000 制造商:Samsung Semiconductor 功能描述:DRAM CHIP DIRECT RDRAM 288MBIT 2.5V 92PIN WBGA - Bulk
K4R881869E-GCM8T00 制造商:Samsung Semiconductor 功能描述:288MRDRAMDIRECT RDRAMX18WBGA - Tape and Reel
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*