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參數資料
| 型號： | K4R271669E |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128Mbit RDRAM(E-die) |
| 中文描述： | 128Mbit的RDRAM（電子模具） |
| 文件頁數： | 5/20頁 |
| 文件大小： | 290K |
| 代理商： | K4R271669E |
Page 3
Direct RDRAM
K4R271669E
Version 1.4 July 2002
Table 2: Pin Description
Signal
I/O
Type
# Pins
center
Description
SIO1,SIO0
I/O
CMOS
a
2
Serial input/output. Pins for reading from and writing to the control regis-
ters using a serial access protocol. Also used for power management.
CMD
I
CMOS
a
1
Command input. Pins used in conjunction with SIO0 and SIO1 for reading
from and writing to the control registers. Also used for power manage-
ment.
SCK
I
CMOS
a
1
Serial clock input. Clock source used for reading from and writing to the
control registers
V
DD
6
Supply voltage for the RDRAM core and interface logic.
V
DDa
1
Supply voltage for the RDRAM analog circuitry.
V
CMOS
2
Supply voltage for CMOS input/output pins.
GND
9
Ground reference for RDRAM core and interface.
GNDa
1
Ground reference for RDRAM analog circuitry.
DQA7..DQA0
I/O
RSL
b
8
Data byte A. Eight pins which carry a byte of read or write data between
the Channel and the RDRAM device.
CFM
I
RSL
b
1
Clock from master. Interface clock used for receiving RSL signals from
the Channel. Positive polarity.
CFMN
I
RSL
b
1
Clock from master. Interface clock used for receiving RSL signals from
the Channel. Negative polarity
V
REF
1
Logic threshold reference voltage for RSL signals
CTMN
I
RSL
b
1
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Negative polarity.
CTM
I
RSL
b
1
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Positive polarity.
RQ7..RQ5 or
ROW2..ROW0
I
RSL
b
3
Row access control. Three pins containing control and address informa-
tion for row accesses.
RQ4..RQ0 or
COL4..COL0
I
RSL
b
5
Column access control. Five pins containing control and address informa-
tion for column accesses.
DQB7..
DQB0
I/O
RSL
b
8
Data byte B.Eight pins which carry a byte of read or write data between
the Channel and the RDRAM device.
NC
2
No Connection.
Total pin count per package
54
a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.
b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
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