- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374277 > K4R271669E (SAMSUNG SEMICONDUCTOR CO. LTD.) 128Mbit RDRAM(E-die) PDF資料下載
參數(shù)資料
| 型號(hào)： | K4R271669E |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128Mbit RDRAM(E-die) |
| 中文描述： | 128Mbit的RDRAM（電子模具） |
| 文件頁數(shù)： | 14/20頁 |
| 文件大小： | 290K |
| 代理商： | K4R271669E |
Page 12
Direct RDRAM
K4R271669E
Version 1.4 July 2002
Timing Conditions
Table 11: Timing Conditions
Symbol
Parameter
Min
Max
Unit
Figure(s)
t
CYCLE
CTM and CFM cycle times (-800)
2.50
3.83
ns
Figure 56
t
CR
, t
CF
CTM and CFM input rise and fall times. Use the minimum value of
these parameters during testing.
0.2
0.5
ns
Figure 56
t
CH
, t
CL
CTM and CFM high and low times
40%
60%
t
CYCLE
Figure 56
t
TR
CTM-CFM differential (MSE/MS=0/0)
CTM-CFM differential (MSE/MS=1/1)
a
0.0
0.9
1.0
1.0
t
CYCLE
Figure 43
Figure 56
t
DCW
Domain crossing window
-0.1
0.1
t
CYCLE
Figure 62
t
DR
, t
DF
DQA/DQB/ROW/COL input rise/fall times (20% to 80%). Use the min-
imum value of these parameters during testing.
0.2
0.65
ns
Figure 57
tS, tH
DQA/DQB/ROW/COL-to-CFM setup/hold @ t
CYCLE
=2.50ns
0.250
b
-
ns
Figure 57
t
DR1,
t
DF1
SIO0, SIO1 input rise and fall times
-
5.0
ns
Figure 59
t
DR2,
t
DF2
CMD, SCK input rise and fall times
-
2.0
ns
Figure 59
t
CYCLE1
SCK cycle time - Serial control register transactions
1000
-
ns
Figure 59
SCK cycle time - Power transitions
10
-
ns
Figure 59
t
CH1
, t
CL1
SCK high and low times
4.25
-
ns
Figure 59
t
S1
CMD setup time to SCK rising or falling edge
c
1.25
-
ns
Figure 59
t
H1
CMD hold time to SCK rising or falling edge
c
1
-
ns
Figure 59
t
S2
SIO0 setup time to SCK falling edge
40
-
ns
Figure 59
t
H2
SIO0 hold time to SCK falling edge
40
-
ns
Figure 59
t
S3
PDEV setup time on DQA5..0 to SCK rising edge.
0
-
ns
Figure 50
t
H3
PDEV hold time on DQA5..0 to SCK rising edge.
5.5
-
ns
Figure 60
t
S4
ROW2..0, COL4..0 setup time for quiet window
-1
-
t
CYCLE
Figure 50
t
H4
ROW2..0, COL4..0 hold time for quiet window
d
5
-
t
CYCLE
Figure 50
t
NPQ
Quiet on ROW/COL bits during NAP/PDN entry
4
-
t
CYCLE
Figure 49
t
READTOCC
Offset between read data and CC packets (same device)
12
-
t
CYCLE
Figure 54
t
CCSAMTOREAD
Offset between CC packet and read data (same device)
8
-
t
CYCLE
Figure 54
t
CE
CTM/CFM stable before NAP/PDN exit
2
-
t
CYCLE
Figure 50
t
CD
CTM/CFM stable after NAP/PDN entry
100
-
t
CYCLE
Figure 49
t
FRM
ROW packet to COL packet ATTN framing delay
7
-
t
CYCLE
Figure 48
t
NLIMIT
Maximum time in NAP mode
10.0
μ
s
Figure 47
t
REF
Refresh interval
32
ms
Figure 52
t
BURST
Interval after PDN or NAP (with self-refresh) exit in which all banks of
the RDRAM device must be refreshed at least once.
200
μ
s
Figure 53
t
CCTRL
Current control interval
34 t
CYCLE
100ms
ms/t
CYCLE
Figure 54
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4R571669D | 256/288Mbit RDRAM(D-die) |
| K4R881869D | 256/288Mbit RDRAM(D-die) |
| K4R761869A-GCN1 | 576Mbit RDRAM (A-die) 1M x 18bit x 32s banks Direct RDRAMTM |
| K4R761869A-GCT9 | 576Mbit RDRAM (A-die) 1M x 18bit x 32s banks Direct RDRAMTM |
| K4R761869A-F | 576Mbit RDRAM (A-die) 1M x 18bit x 32s banks Direct RDRAMTM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4R271669F | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit RDRAM(F-die) |
| K4R271669F-RCS8000 | 制造商:Samsung 功能描述:128 DIRECT RDRAM X16 WBGA - Trays |
| K4R271669F-TCS8000 | 制造商:Samsung 功能描述:128 DIRECT RDRAM X16 WBGA - Trays |
| K4R271669H-DCS8000 | 制造商:Samsung Semiconductor 功能描述:128MRDRAMDIRECT RDRAMX16FBGA - Bulk |
| K4R271669H-DCS8T00 | 制造商:Samsung Semiconductor 功能描述:128MRDRAMDIRECT RDRAMX16FBGA - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。